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AT86RF212 low power 700/800/900 mhz transceiver for ieee 802.15.4, p802.15.4c draft amendment, zigbee, 6lowpan, and ism applications preliminary 8168b-mcu wireless-02/09 features ? fully integrated 700/800/900 mhz-band transceiver - chinese wpan band from 779 to 787 mhz - european srd band from 863 to 870 mhz - north american ism band from 902 to 928 mhz ? direct sequence spread spectrum with different modulation schemes and data rates - bpsk with 20 and 40 kbit/s, compliant to ieee 802.15.4-2006 - o-qpsk with 100 and 250 kbit/s, compliant to ieee 802.15.4-2006 - o-qpsk with 250 kbit/s, compliant to ieee p802.15.4c - o-qpsk with 200, 400, 500, and 1000 kbit/s psdu data rate ? flexible combination of frequency bands and data rates ? industry leading link budget - receiver sensitivity up to -110 dbm - programmable tx output power up to +10 dbm ? low power supply voltage from 1.8 v to 3.6 v - internal voltage regulators and battery monitor ? low current consumption - sleep = 0.2 a - trx_off = 0.4 ma - rx_on = 9.0 ma - busy_tx = 18 ma at p tx = 5 dbm ? digital interface - registers, frame buffer, and aes accessible through spi - clock output with configurable rate ? radio transceiver features - adjustable receiver sensitivity - integrated tx/rx switch, lna, and pll loop filter - fast settling pll supporting frequency hopping - automatic vco and filter calibration - integrated 16 mhz crystal oscillator - 128 byte fifo for transmit/receive ? ieee 802.15.4-2006 hardware support - fcs computation and check - clear channel assessment - received signal strength indicator, en ergy detection, and link quality indication ? mac hardware accelerator - automatic acknowledgement and retransmission - csma-ca and lbt - automatic frame filtering ? aes 128 bit hardware accelerator (ecb and cbc modes) ? extended feature set hardware support - true random number generation for security applications - tx/rx indication (external rf front end control) ? optimized for low bom cost and ease of production - low external component count: antenna, reference crystal, and bypass capacitors - excellent esd robustness ? industrial temperature range from -40c to +85c ? 32-pin low-profile lead-free plastic qfn package, 5.0 x 5.0 x 0.9 mm 3 ? compliant to ieee 802.15.4-2003, ieee 802.15.4-2006, ieee p802.15.4c, etsi en 300 220-1, and fcc 47 cfr section 15.247
2 8168b-mcu wireless-02/09 AT86RF212 1 overview the AT86RF212 is a low-power, low-voltage 700/800/900 mhz transceiver specially designed for the ieee standard 8 02.15.4, zigbee, 6lowpan, and high data rate ism applications. for the sub-1 ghz bands, it s upports low data rates (20 and 40 kbit/s) of the ieee standard 802.15.4-2003 [2] and prov ides optional data rates (100 and 250 kbit/s) using o-qpsk, according to t he ieee standard 802.15.4-2006 [1] and the respective ieee p802.15.4c draft amendment [3]. furthermore, proprietary high data rate modes up to 1000 kbit/s can be employed. the AT86RF212 is a true spi-to-antenna soluti on. rf-critical components except the antenna, crystal, and de-coupling capaci tors are integrated on-chip. mac and aes hardware accelerators improve overall system power efficiency and timing. 1.1 general circuit description the AT86RF212 single-chip rf transceiver provides a complete radio interface between the antenna and the microcontroller. it comprises the analog radio part, digital modulation and demodulation including time and frequency synchronization, as well as data buffering. the number of external com ponents is minimized so that only the antenna, a filter (at high output power levels ), the crystal, and four bypass capacitors are required. the bidirectional differentia l antenna pins are used in common for rx and tx, i.e. no external antenna switch is needed. control of an external power amplifier is supported by two digital control signals (differential operation). the transceiver block diagram is shown in figure 1-1. the re ceiver path is based on a low-if arch itecture. after channel filtering and down- conversion the low-if signal is sampled and applied to the digital signal processing part. communication between transmitter and receiver is based on direct sequence spread spectrum with different modulation schemes and spreading codes. the AT86RF212 supports the ieee 802.15.4-2006 standard mandatory bpsk modulation and optional o-qpsk modulation in the 868. 3 mhz and 915 mhz bands. in addition it supports the o-qpsk modulation defined in ieee p802.15. 4c for the chinese 780 mhz band. for applications not necess arily targeting ieee compliant networks the radio transceiver supports prop rietary high data rate modes based on o-qpsk. a single 128 byte trx buffer stores receive or transmit data. the AT86RF212 features hardware supported 128 bit security operation. the standalone aes encryptio n/decryption engine can be accessed in parallel to all phy operational modes. configuration of the AT86RF212, reading, and writing of data memory as well as the aes hardware engine are controlled by the spi interface and additional control signals. on-chip low-dropout voltage regulators provide the analog and digital 1.8 v power supply. control registers retain their settings in sleep mode when the regulators are turned off. the rx and tx si gnal processing paths are highl y integrated and optimized for low power consumption.
3 8168b-mcu wireless-02/09 AT86RF212 figure 1-1. AT86RF212 block diagram xtal1 xtal2 voltage regulator lna frequency synthesis ppf bpf adc agc rx bbp tx power trx buffer configuration registers spi (slave) tx bbp irq clkm dig1 /rst slp_tr /sel miso mosi sclk rfn dig2 ftn, batmon xosc analog domain digital domain mixer mixer lpf dac pa rfp aes control logic dig3/4
4 8168b-mcu wireless-02/09 AT86RF212 2 pin configuration 2.1 pin-out diagram figure 2-1. AT86RF212 pin-out diagram 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 AT86RF212 clkm dvss dig3 dig4 avss avss rfp rfn dvss /rst dig1 dig2 slp_tr dvss dvdd dvdd devdd dvss sclk miso dvss mosi /sel irq xtal2 xtal1 avss evdd avdd avss avss avss 31 30 29 28 27 26 25 9 10111213141516 avss exposed paddle note: the exposed paddle is electrically connected to the die inside the package. it shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability. 2.2 pin description table 2-1. pin description pins name type description 1 dig3 digital output rx/tx indication, see section 9.4; if disabled, internally pulled to avss 2 dig4 digital output rx/tx indica tion (dig3 inverted), see section 9.4; if disabled, internally pulled to avss 3 avss ground ground for rf signals 4 rfp rf i/o differential rf signal 5 rfn rf i/o differential rf signal 6 avss ground ground for rf signals 7 dvss ground digital ground 8 /rst digital input chip reset; active low 9 dig1 digital output antenna diversity rf switch control, see section 9.3; if disabled, internally pulled to dvss
5 8168b-mcu wireless-02/09 AT86RF212 pins name type description 10 dig2 digital output 1. antenna diversity rf switch control (dig1 inverted), see section 9.3 2. signa l irq_2 (rx_start) for rx frame time stamping, see section 9.5 if disabled, internally pulled to dvss 11 slp_tr digital input controls sleep, transmit start, receive states; active high, see section 4.6 12 dvss ground digital ground 13 dvdd analog regulated 1.8 v internal suppl y voltage; digital domain, see section 7.5 14 dvdd analog regulated 1.8 v internal suppl y voltage; digital domain, see section 7.5 15 devdd supply external supply voltage; digital domain 16 dvss ground digital ground 17 clkm digital output master clock signa l output; low if disabled, see section 7.7 18 dvss ground digital ground 19 sclk digital input spi clock 20 miso digital output spi data out put (master input slave output) 21 dvss ground digital ground 22 mosi digital input spi data in put (master output slave input) 23 /sel digital input spi select, active low 24 irq digital output 1. interrupt request signal; active high or active low, see section 4.7 2. buffer-level mode indicator; active high 25 xtal2 analog crystal pin, see sections 2.2.1.3 and 7.7 26 xtal1 analog crystal pin or external clock supply, see section 2.2.1.3 and 7.7 27 avss ground analog ground 28 evdd supply external supply voltage; analog domain 29 avdd analog regulated 1.8 v internal su pply voltage; analog domain, see section 7.5 30 avss ground analog ground 31 avss ground analog ground 32 avss ground analog ground paddle avss ground analog ground; exposed paddle of qfn package 2.2.1 analog and rf pins 2.2.1.1 supply a nd ground pins evdd, devdd evdd and devdd are analog and digital suppl y voltage pins of the AT86RF212 radio transceiver. avdd, dvdd avdd and dvdd are outputs of the internal voltage regulators and require bypass capacitors for stable operation. the voltage regulators are controlled independently by the radio transceivers state machine and ar e activated depending on the current radio transceiver state. the voltage regulators c an be configured for external supply. for details refer to section 7.5. avss, dvss avss and dvss are anal og and digital ground pins respectively.
6 8168b-mcu wireless-02/09 AT86RF212 2.2.1.2 rf pins rfn, rfp a differential rf port (rfp/rfn) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. at board-level, the differential rf layout ensures high receiver sensitivity by reducing spurious emissions originated from other digital ics such as a microcontroller. the rf port is designed for a 100 differential load. a dc path between the rf pins is allowed. a dc path to ground or supply vo ltage is not allowed. therefore when connecting a rf-load providing a dc path to the power supply or ground, ac-coupling is required as indicated in table 2-2. a simplified schem atic of the rf front end is shown in figure 2-2. figure 2-2. simplified rf front-end schematic lna pa rfp rfn rxtx 0.9v tx rx cm feedback m0 AT86RF212 pcb mc rf port dc values depend on the operating state, refer to section 5. in trx_off state, whe n the analog front-end is disabled (see section 5.1.2.3), the rf pins are pulled to grou nd, preventing a floating voltage larger than 1.8 v, which is not allowed for the internal circuitry. in transmit mode, a control loop provides a common-mode voltage of 0.9 v. transistor m0 is off, allowing the pa to set t he common-mode voltage. the common-mode capacitance at each pin to ground shall be < 100 pf to en sure the stability of this common-mode feedback loop. in receive mode, the rf port provides a low-impedance path to ground when transistor m0, see figure 2-2, pulls the inductor center ta p to ground. a dc voltage drop of 20 mv across the on-chip inductor can be measured at the rf pins. matching control (mc) is implemented by an adjustable capacitance to ground at each rf pin as shown in figure 2-2. the input capacitance can be changed within 15 steps by setting a 4 -bit control word (register 0x19, rf_ctrl_1).
7 8168b-mcu wireless-02/09 AT86RF212 2.2.1.3 crystal oscillator pins xtal1, xtal2 the pin xtal1 is the input of the referenc e oscillator amplifier (xosc), xtal2 the output. a detailed description of the cr ystal oscillator setup and the related xtal1/xtal2 pin configurat ion can be found in section 7.7. whe n using an external clock reference signal, xtal1 shall be used as input pin. for further details refer to section 7.7.3. 2.2.1.4 analog pin sum mary table 2-2. analog pin behavior ? dc values pin values and conditions comments rfp/rfn v dc = 0.9 v (busy_tx) v dc = 20 mv (receive states) v dc = 0 mv (otherwise) dc level at pins rfp/rfn for various transceiver states ac-coupling is required if an antenna with a dc path to ground is used. serial capacitance and capac itance of each pin to ground must be < 100 pf. xtal1/xtal2 v dc = 0.9 v at both pins c par = 3 pf v ac 1.0 vpp dc level at pins xtal1/xtal2 for various transceiver states parasitic capacitance (c par ) of the pins must be considered as additional load capacitance to the crystal. dvdd v dc = 1.8 v (all states, except p_on, sleep, and reset) v dc = 0 mv (otherwise) dc level at pin dvdd for various transceiver states supply pins (voltage regulator output) for the digital 1.8 v voltage domain. the outputs shall be bypassed by 1 f. avdd v dc = 1.8 v (all states, except p_on, sleep, reset, and trx_off) v dc = 0 mv (otherwise) dc level at pin avdd for various transceiver states supply pin (voltage regulator out put) for the analog 1.8 v voltage domain. the outputs shall be bypassed by 1 f. 2.2.2 digital pins the at86 rf212 provides a digital microcontro ller interface. the interface comprises a slave spi (/sel, sclk, mosi and miso) and additional control signals (clkm, irq, slp_tr, /rst and dig2). the microcontroller in terface is described in detail in chapter 4. additional dig ital output signals dig1 ? dig4 are provided to control external blocks, i.e. for antenna diversity rf switch contro l or as an rx/tx indicator, see sections 9.3 and 9.4, respectively. after reset, these pins are connected to digital ground (dig 1/dig2) or analog ground (dig3/dig4). 2.2.2.1 driver strength settings the driver strength of all digital output pins (miso, irq, dig1, ?, dig4) and clkm pin can be configured using regist er 0x03 (trx_ctrl_0), see table 2-3. table 2-3. di gital output driver configuration pin default driver strength comment miso, irq, dig1, ?, dig4 2 ma adjustable to 2 ma, 4 ma, 6 ma, and 8 ma clkm 4 ma adjustable to 2 ma, 4 ma, 6 ma, and 8 ma the capacitive load should be as small as possible and not larger than 50 pf when using the 2 ma minimum driver strength setti ng. generally, the output driver strength should be adjusted to the lowest possible value in order to keep the current consumption and the emission of digital signal harmonics low.
8 8168b-mcu wireless-02/09 AT86RF212 2.2.2.2 pull-up and pull-down configuration pulling resistors are internally connected to all digital input pins in radio transceiver state p_on, see section 5.1.2.1. table 2-4 summarizes the pull-up and pull-down config uration. table 2-4. pull-up / pull-down configuration of digital input pins in p_on state pins h = pull-up, l = pull-down /rst h /sel h sclk l mosi l slp_tr l in all other states including reset, no pull-up or pull-down resistors are connected to any of the digital input pins. 2.2.2.3 register description register 0x03 (trx_ctrl_0) : the trx_ctrl_0 register controls the driv e current of the digital output pads and the clkm clock rate. table 2-5. register 0x03 (trx_ctrl_0) bit 7 6 5 4 name pad_io[1] pad_io[0] pad_io_clkm[1] pad_io_clkm[0] read/write r/w r/w r/w r/w reset value 0 0 0 1 bit 3 2 1 0 name clkm_sha_sel clkm_ctrl clkm_ctrl clkm_ctrl read/write r/w r/w r/w r/w reset value 1 0 0 1 ? bit 7:6 ? pad_io these register bits set the output driver cu rrent of digital output pads, except clkm. table 2-6. digital output driver strength register bits value description 0 (1) 2 ma 1 4 ma 2 6 ma pad_io 3 8 ma note: 1. underlined values indicate reset settings.
9 8168b-mcu wireless-02/09 AT86RF212 ? bit 5:4 ? pad_io_clkm these register bits set the output driver current of pin clkm. refer also to section 7.7. table 2-7. clkm drive r strength register bits value description 0 2 ma 1 4 ma 2 6 ma pad_io_clkm 3 8 ma ? bit 3 ? clkm_sha_sel refer to section 7.7. ? bit 2:0 ? cl km_ctrl refer to section 7.7.
10 8168b-mcu wireless-02/09 AT86RF212 3 application circuits 3.1 basic application schematic a basic application schematic of the at86rf2 12 with a single-ended rf connector is shown in figure 3-1. the 50 ? single -ended rf input is transformed to the 100 ? differential rf port impedance using balun b1. the capacitors c1 and c2 provide ac coupling of the rf input to the rf port. r egulatory rules like fcc 47 section 15.247, erc/rec 70-03 or etsi en 300 220 may require an external filter f1, depending on used transmit power levels. figure 3-1. basic application schematic 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 25 26272829303132 AT86RF212 dig3 avss dig4 avss avss rfp rfn avss dvss dig1 dig2 slp_tr dvss dvdd dvdd xtal2 devdd dvss avss avdd evdd avss xtal1 17 18 19 20 21 22 23 24 dvss clkm irq miso dvss mosi sclk cb3 cb4 xtal cx1 cx2 cb1 cb2 rf digital interface v dd /rst /sel c1 c2 b1 f1 c3 r1 the power supply bypass capacitors (cb2, cb 4) are connected to the external analog supply pin (evdd, pin 28) and external digi tal supply pin (devdd, pin 15). capacitors cb1 and cb3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. all by pass capacitors should be placed as close
11 8168b-mcu wireless-02/09 AT86RF212 as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance. the crystal (xtal), the two load capacitors (cx1, cx2), and the internal circuitry connected to pins xtal1 and xtal2 form the crystal oscilla tor. to achieve the best accuracy and stability of the reference frequency, large parasitic capacitances should be avoided. crystal lines should be routed as short as possible and not in proximity of digital i/o signals. this is especially required for the high data rate modes, refer to chapter 7.1.4. crosstalk from digital signals on the crystal pins or the rf pins can degrade the system performance. therefore, a low-pass filter (c3, r1) is placed close to the clkm output pin to reduce the emissi on of clkm signal harmonics. this is not needed if the clkm pin is not used as a microcontroller clock source. in that case, the output should be turned off during device initialization. the ground plane of the application board sh ould be separated into four independent fragments, the analog, the digital, the antenna and the xtal ground plane. the exposed paddle shall act as the reference point of the individual grounds. table 3-1. example bill of materials (bom ) for basic application schematic symbol description value manufacturer part number comment b1 smd balun 900 mhz wuerth jti 748431090 0900bl18b100 f1 smd low pass filter 900 mhz wuerth jti 748131009 0915lp15a026 b1 + f1 balun/filter combination 900 mhz jti 0892fb15a0100 cb1, cb3 ldo vreg bypass capacitor 1 f cb2, cb4 power supply bypass capacitor 1 f avx murata 0603yd105kat2a grm188r61c105ka12d x5r (0603) 10% 16 v cx1, cx2 crystal load capacitor 12 pf avx murata 06035a120ja grp1886c1h120ja01 cog (0603) 5% 50 v cog 5% c1, c2 rf coupling capacitor 68 pf epcos epcos avx b37930 b37920 06035a680jat2a (0402 or 0603) 50 v cog (0603) 0.5 pf 50 v c3 clkm low-pass filter capacitor 2.2 pf avx murata 06035a229da grp1886c1h2r0da01 designed for f clkm = 1 mhz r1 clkm low-pass filter resistor 680 designed for f clkm = 1 mhz xtal crystal cx-4025 16 mhz sx-4025 16 mhz acal taitien siward xwbbpl-f-1 a207-011 3.2 extended feature set application schematic for using the extended features ? antenna diversity uses pins dig1/dig2 (1) section 9.3 ? rx/tx indicator uses pins dig3/dig4 section 9.4 ? rx frame time stamping uses pin dig2 section 9.5 an extended application schematic is required. all other extended features (see section 9) do not need an extended schematic.
12 8168b-mcu wireless-02/09 AT86RF212 an extended feature set application schemat ic illustrating the use of the AT86RF212 extended feature set is shown in figure 3-2. although this example shows all addition al hardware features combined, it is possible to use all features separately or in various combinations. figure 3-2. extended feature application schematic 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 2526 27 28 2930 31 32 AT86RF212 dig3 avss dig4 avss avss rfp rfn avss dvss dig1 dig2 slp_tr dvss dvdd dvdd xtal2 devdd dvss avss avdd evdd avss xtal1 17 18 19 20 21 22 23 24 dvss clkm irq miso dvss mosi sclk cb3 cb4 xtal cx1 cx2 cb1 cb2 digital interface v dd /rst /sel c1 c2 b1 f1 c3 r1 rf- switch ant0 ant1 rf- switch sw1 sw2 pa lna n1 n2 in this example, a balun (b1) transforms the differential radio transceiver rf pins (rfp/rfn) to a single ended rf signal, sim ilar to the basic application schematic; refer to figure 3-1. the rf-switches (sw1, sw2) separate between receive and transmit path in an external rf front-end. these switches are controlled by the rx/tx indicator, represented by the differential pin pair dig3/dig4, refer to 9.4. duri ng receive the corresponding microcontro ller may search for the most reliable rf signal path using an antenna diversity algorithm or stored statistic data of link signal quality. one antenna is selected (sw2) by the antenna diversity rf switch control pin dig1 (1) , the rf signal is amplified by an optional low-noise amplifier (n2) and fed to the radio transceiver using the second rx/tx switch (sw1). during transmit the AT86RF212 tx signal is amplified using an external pa (n1), low pass filtered to suppress spur ious harmonics emission and fed to the antennas via an rf switch (sw2). in this example rf switch sw2 further supports antenna diversity controlled by pin dig1 (1) . note: 1. dig1/dig2 can be used as a differential pin pair to control an rf switch if rx frame time stamping is not used, refer to sections 9.3 and 9.5, respectively.
13 8168b-mcu wireless-02/09 AT86RF212 4 microcontroller interface 4.1 overview this section describes the AT86RF212 to microcontroller interface. the interface comprises a slave spi and additional control signals; see figure 4-1. the spi timing and protocol are de scribed below. figure 4-1. microcontroller to AT86RF212 interface microcontroller AT86RF212 /sel mosi miso sclk clkm irq slp_tr mosi miso sclk gpio1/clk gpio2/irq gpio3 mosi miso sclk clkm irq slp_tr /rst gpio4 spi /sel /sel /rst dig2 gpio5 dig2 spi - master spi - slave microcontrollers with a master spi such as at mel?s avr family interface directly to the AT86RF212. the spi is used for register, frame buffer, sram, and aes access. the additional control signals are connected to the gpio/irq interface of the microcontroller. table 4-1 introduces the radio transcei ver i/o sign als and their functionality. table 4-1. signal description of microcontroller interface signal description /sel spi select signal, active low mosi spi data (master out put slave input) signal miso spi data (master i nput slave output) signal sclk spi clock signal clkm clock output, refer to section 7.7.4, usable as: - microcontroller clock source - high precision timing reference - mac timer reference irq interrupt request signal, further used as: - frame buffer empty indi cator, refer to section 9.6. slp_tr multi purpose control signal, see section 4.6: - sleep/wakeup - tx start - disable/enable clkm
14 8168b-mcu wireless-02/09 AT86RF212 signal description /rst AT86RF212 reset signal, active low dig2 multi purpose control signal, amongst others to signal the reception of a frame, see section 9.5. 4.2 spi timing description pin 17 (clkm) can be used as a microcontroller master clock source. if the microcontroller derives the spi master cl ock (sclk) directly from clkm, the spi operates in synchronous mode, ot herwise in asynchronous mode. in synchronous mode, the maximum sclk frequency is 8 mhz. in asynchronous mode, the maximum sclk fr equency is limited to 7.5 mhz. the signal at pin clkm is not required to derive sclk and may be disabled to reduce power consumption and spurious emissions. figure 4-2 and figure 4-3 illustrate the spi timing and introduces its parameters. the corre sponding timing parameter definitions t 1 ? t 9 are defined in section 10.4. figure 4-2. spi timing, global map, an d definition of timing parameters t 5 , t 6 , t 8 and t 9 sclk t 8 mosi 6 7 5 4 3 2 1 0 6 7 5 4 3 2 1 0 miso bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 bit 4 bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 bit 4 bit 7 t 6 bit 7 t 5 /sel t 9 figure 4-3. spi timing, detailed drawing of timing parameter t 1 to t 4 bit 7 bit 6 t 1 t 2 bit 5 t 4 t 3 bit 7 bit 6 bit 5 sclk mosi miso /sel the spi is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. the spi master starts the transfer by asserting /sel = l. then the master generat es eight spi clock cycles to transfer one byte to the radio transceiver (via mosi). at the same time, the slave transmits one byte to the master (via miso). when the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. all bytes are transferred with msb first. an spi transaction is finished by releasing /sel = h.
15 8168b-mcu wireless-02/09 AT86RF212 /sel = l enables the miso output driver of the AT86RF212. the msb of miso is valid after t 1 (see section 10.4, parameter 10.4.3) and is updated at each falling edge of sclk. if the driver is disabled, there is no internal pull-up resistor connected to it. driving the appropriate signal level must be ensured by the master device or an external pull-up resistor. note, when both /sel and /rst are active, the miso output driver is also enabled. referring to figure 4-2 and figure 4-3 mosi is sampled at the rising edge of the sclk sign al and the output is set at the falling edge of sclk. the signal must be stable before and after the rising edge of sclk as specified by t 3 and t 4 , refer to section 10.4, para meters 10.4.5 and 10.4.6. this spi operational mod e is commonly known as ? spi mode 0 ?. 4.3 spi protocol each spi sequence starts with transferri ng a command byte from the spi master via mosi (see table 4-2) with msb first. this command byte defines the spi access mode and ad ditional mode-dependent information. table 4-2. spi command byte definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access mode access type 1 0 register address [5:0] read access 1 1 register address [5:0] register access write access 0 0 1 reserved read access 0 1 1 reserved frame buffer access write access 0 0 0 reserved read access 0 1 0 reserved sram access write access each spi transfer returns bytes back to the spi master on miso. the content of the first byte is the phy_status field, see section 4.4. in figure 4-4 to figure 4-14 and the following chapters logic values stated with xx on mosi are ig nored by the radio transceiver, but need to have a valid logic level. return values on miso stated as xx shall be ignored by the microcontroller. the different access modes are described within the following sections. 4.3.1 register access mode a registe r access mode is a two-byte read/wr ite operation initiated by /sel = l. the first transferred byte on mosi is the command byte including an identifier bit (bit7 = 1), a read/write select bit (bit 6), and a 6-bit register address. on read access, the content of the selected register address is returned in the second byte on miso (see figure 4-4). figure 4-4. registe r access mode ? read access 1 address[5:0] 0 xx mosi phy_status (1) read data[7:0] miso byte 1 (command byte) byte 2 (data byte)
16 8168b-mcu wireless-02/09 AT86RF212 note: 1. each spi access can be configured to return phy status information (phy_status ) on miso, refer to section 4.4. on write access, the second byte transferr ed on mosi contains the write data to the selected address (see figure 4-5). figure 4-5. registe r access mode ? write access 1 address[5:0] 1 write data[7:0] mosi phy_status xx miso byte 1 (command byte) byte 2 (data byte) each register access must be terminated by setting /sel = h. figure 4-6 illustrates a typical spi sequence for a registe r access sequence for write and read respectively. figure 4-6. example spi sequence ? register access mode phy_status xx phy_status read data write command write data read command xx register write access register read access sclk mosi miso /sel 4.3.2 frame buffer access mode the 12 8-byte frame buffer can hold the phy service data unit (psdu) data of one ieee 802.15.4 compliant rx or one tx frame of maximum length at a time. a detailed description of the frame buffer can be found in section 7.4. an introduction to the ieee 802.15.4 frame form at can be found in section 6.1. frame buffer read and write accesses are used to read or write frame data (psdu and additional information) from or to the frame buffer. each access starts with /sel = l followed by a command byte on mosi. if this byte indicates a frame read or write access, the next byte phr indicates the frame length followed by the psdu data, see figure 4-7 and figure 4-8. on f rame buffer read access, phy header (phr) and psdu are transferred via miso starting with the second byte. after the ps du data, three more bytes are transferred containing the link quality indication (lqi) value, the energy detection (ed) value, and the status information (rx_status) of the received frame. figure 4-7 illustrates the packet struct ure of a frame buffer read ac cess. the structure of rx_status is described in table 4-3.
17 8168b-mcu wireless-02/09 AT86RF212 figure 4-7. packet structure - frame read access 0 reserved[5:0] 0 mosi phy_status miso byte 1 (command byte) 1 xx phr[7:0] byte 2 (data byte) xx psdu[7:0] byte 3 (data byte) xx ed[7:0] byte n-1 (data byte) xx rx_status[7:0] byte n (data byte) xx lqi[7:0] byte n-2 (data byte) table 4-3. rx_status bit 7 6 5 4 content rx_crc_valid (register 0x06, phy_rssi) trac_status (register 0x02, trx_state) reference section 6.3.5 section 5.2.6 bit 3 2 1 0 content reserved reference reserved note, the frame buffer read access can be terminated at any time without any consequences by setting /sel = h, e.g. after reading the frame length byte only. a successive frame buffer read operation starts again at the phr field. on frame buffer write access the second byte transferred on mosi contains the frame length (phr field) followed by the payload data (psdu) as shown by figure 4-8. figure 4-8. packet structu re - frame write access 0 reserved[5:0] 1 mosi phy_status miso byte 1 (command byte) 1 phr[7:0] xx byte 2 (data byte) psdu[7:0] xx byte 3 (data byte) psdu[7:0] xx byte n -1 (data byte) psdu[7:0] xx byte n (data byte) the number of bytes n for one frame buffer access is calculated as follows: read access : n = 5 + frame_length [phy_status, phr, psdu data, lqi, ed, and rx_status] write access : n = 2 + frame_length [command byte, phr, and psdu data] the maximum value of frame_length is 127 bytes. that means that n 132 for frame buffer read and n 129 for frame buffer write accesses. each read or write of a data byte automatic ally increments the address counter of the frame buffer until the access is terminated by setting /sel = h. figure 4-9 and figure 4-10 illustrate an example spi sequence of a frame buffer access to read a frame with 2-byte psd u and write a frame with 4-byte psdu.
18 8168b-mcu wireless-02/09 AT86RF212 figure 4-9. example spi sequence - frame buffer read of a frame with 2-byte psdu command xx xx xx xx xx phy_status phr psdu 2 psdu 1 ed lqi xx rx_status sclk mosi miso /sel figure 4-10. example spi sequence - frame buffer write of a frame with 4-byte psdu command phr psdu 1 psdu 2 psdu 3 psdu 4 phy_status xx xx xx xx xx sclk mosi miso /sel access violations during a frame buffer read or write access are indicated by interrupt irq_6 (trx_ur). for further details, refer to section 7.4. notes ? the frame buffer is shared between rx and tx; therefore, the frame data are overwritten by new incoming frames. if the tx frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile. ? to avoid overwriting during receive dynamic frame buffer protection can be enabled, refer to section 9.7. ? for exceptions, e.g. receiving acknowled gement frames in extended operating mode (tx_aret) refer to section 5.2.4. 4.3.3 sram access mode the s ram access mode allows accessing dedicated bytes within the frame buffer. this may reduce the spi traffic. during frame receive after occurrence of irq_2 (rx_start) an sram access can be used to upload the phr field while preser ving dynamic frame buffer protection, see 9.7. e ach sram access starts with /sel = l. t he first transferred byte on mosi shall be the command byte and must indicate an sram access mode according to the definition in table 4-2. the following byte indicates the st art a ddress of the write or read access. the address space is 0x00 to 0x7f for radi o transceiver receive or transmit operations. the security module (aes) uses an address space from 0x82 to 0x94, refer to section 9.1. on sram read a ccess, one or more bytes of read data are transferred on miso starting with the third byte of the access sequence (see figure 4-11).
19 8168b-mcu wireless-02/09 AT86RF212 figure 4-11. packet structure ? sram read access 0 reserved[5:0] 0 mosi phy_status miso byte 1 (command byte) 0 address[7:0] xx byte 2 (address) xx data[7:0] byte 3 (data byte) xx data[7:0] byte n -1 (data byte) xx data[7:0] byte n (data byte) on sram write access, one or more bytes of write data are transferred on mosi starting with the third byte of the access sequence (see figure 4-12). do not attempt to read o r write bytes beyond the sram buffer size. figure 4-12. packet structure ? sram write access 0 reserved[5:0] 1 mosi phy_status miso byte 1 (command byte) 0 address[7:0] xx byte 2 (address) data[7:0] xx byte 3 (data byte) data[7:0] xx byte n -1 (data byte) data[7:0] xx byte n (data byte) as long as /sel = l, every subsequent byte read or byte write increments the address counter of the frame buffer until the sram access is terminated by /sel = h. figure 4-13 and figure 4-14 illustrate an example spi sequence of a sram access to read and write a data package of 5-byte length respectively. figure 4-13. example spi sequence ? sram read access of a 5-byte data package command address xx xx xx xx phy_status xx data 2 data 1 data 4 data 3 xx data 5 sclk mosi miso /sel figure 4-14. example spi sequence ? sram write access of a 5-byte data package command address data 1 data 2 data 3 data 4 phy_status xx xx xx xx xx data 5 xx sclk mosi miso /sel notes ? the sram access mode is not intended to be used as an alternative to the frame buffer access modes (see section 4.3.2). ? frame buffer access violations are not i ndicated by a trx_ur interrupt when using the sram access mode, for further details refer to section 7.4.3.
20 8168b-mcu wireless-02/09 AT86RF212 4.4 phy status information each spi access can be configured to return status information of the radio transceiver ( phy_status ) to the microcontroller using the first byte of the data transferred via miso. the content of the radio transceiver status information can be configured using register bits spi_cmd_mode (register 0x04, trx_ct rl_1). after reset, the content on the first byte send on miso to the microcontroller is set to 0x00. 4.4.1 register description ? spi control regis ter 0x04 (trx_ctrl_1) : the trx_ctrl_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. table 4-4. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode irq_mask_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en refer to section 9.4.3. ? bit 6 ? irq _2_ext_en refer to section 9.5.2. ? bit 5 ? tx_ auto_crc_on refer to section 6.3.5. ? bit 4 ? rx_ bl_ctrl refer to section 9.6.2. ? bit 3:2 ? spi_cm d_mode each spi transfer returns bytes back to the spi master. the content of the first byte can be configured using register bits spi_cmd_mode. the transfer of the following status information can be configured as follows: table 4-5. phy status information register bits value description 0 default (empty, all bits 0x00) 1 monitor trx_status register see 5.1.5 2 monitor phy_rssi register see 6.4 spi_cmd_mode 3 monitor irq_status register see 4.7 interrupts are n ot cleared.
21 8168b-mcu wireless-02/09 AT86RF212 ? bit 1 ? irq_mask_mode refer to section 4.7.2. ? bit 0 ? irq _polarity refer to section 4.7.2. 4.5 radio transceiver identification the AT86RF212 can be identified by four regist ers. one register contains a unique part number and one register the corresponding ve rsion number. additional two registers contain the jedec manufacture id. 4.5.1 register description r egister 0x1c (part_num) : table 4-6. register 0x1c (part_num) bit 7 6 5 4 3 2 1 0 name part_num[7:0] read/write r reset value 0 0 0 0 0 1 1 1 ? bit 7:0 ? part_num this register contains the radio transceiver part number. table 4-7. radio transceiver part number register bits value state description part_num 7 AT86RF212 part number register 0x1d (version_num) : table 4-8. register 0x1d (version_num) bit 7 6 5 4 3 2 1 0 name version_num[7:0] read/write r reset value 0 0 0 0 0 0 0 1 ? bit 7:0 ? version_num this register contains the r adio transceiver version number. table 4-9. radio transceiver version number register bits value state description version_num 1 revision a register 0x1e (man_id_0) : table 4-10. register 0x1e (man_id_0)
22 8168b-mcu wireless-02/09 AT86RF212 bit 7 6 5 4 3 2 1 0 name man_id_0[7:0] read/write r reset value 0 0 0 1 1 1 1 1 ? bit 7:0 ? man_id_0 bits [7:0] of the 32-bit jedec manufacturer id are stored in register bits man_id_0. bits [15:8] are stored in register 0x1f (man _id_1). the highest 16 bits of the id are not stored in registers. table 4-11. jedec manufacturer id ? bits [7:0] register bits value state description man_id_0 0x1f atmel jedec manufacturer id, bits [7:0] of 32 bit manufacturer id: 00 00 00 1f register 0x1f (man_id_1) : table 4-12. register 0x1f (man_id_1) bit 7 6 5 4 3 2 1 0 name man_id_1[7:0] read/write r reset value 0 0 0 0 0 0 0 0 ? bit 7:0 ? man_id_1 bits [15:8] of the 32-bit jede c manufacturer id are stored in register bits man_id_1. bits [7:0] are stored in register 0x1e (man_i d_0). the higher 16 bits of the id are not stored in registers. table 4-13. jedec manufacturer id ? bits [15:8] register bits value state description man_id_1 0x00 atmel jedec manufacturer id bits [15:8] of 32 bit manufacturer id: 00 00 00 1f 4.6 sleep/wake-up and transmit signal (slp_tr) pin 11 (slp_tr) is a multi-functional pin. its function relates to the current state of the AT86RF212 and is summarized in table 4-14. the radio transceive r states are explained in detail in section 5. in state s pll_on and tx_aret_on, pin slp_tr is used as trigger input to initiate a tx transaction. here pin slp_tr is sensitive on rising edge only. after initiating a state change by a rising edg e at pin slp_tr in radio transceiver states trx_off, rx_on or rx_aack_on, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge.
23 8168b-mcu wireless-02/09 AT86RF212 table 4-14. slp_tr multi-functional pin transceiver status function transition description pll_on tx start l ? h starts frame transmission tx_aret_on tx start l ? h starts tx_aret transaction busy_rx_aack tx start l ? h starts ack transmission during rx_aac k slotted operation, see section 5.2.3.5. trx_off sleep l ? h takes the radio transceiver in to sleep state, clkm disabled sleep wakeup h ? l takes the radio transceiver back in to trx_off state, level sensitive rx_on disable clkm l ? h takes the radio transceiver into rx_on_noclk state and disables clkm rx_on_noclk enable clkm h ? l takes the radio transceiver in to rx_on state and enables clkm rx_aack_on disable clkm l ? h takes the radio transceiver into rx_aack_on_noclk state and disables clkm rx_aack_on_noclk enable clkm h ? l takes the radio transceiver into rx_aack_on state and enables clkm sleep state the sleep state is used when radio transceiver functionality is not required, and thus the AT86RF212 can be powered down to reduce the overall power consumption. a power-down scenario is shown in figure 4-15. when the radio transceiver is in trx_off state the microcon troller forces the AT86RF212 to sleep by setting slp_tr = h. if pin 17 (clkm) provides a cl ock to the microcontroller this clock is switched off after 35 clock cycles. this ena bles a microcontroller in a synchronous system to complete its power-down rout ine and prevent deadlock situations. the AT86RF212 awakes when the microcontroller releases pin slp_tr. this concept provides the lowest possible power consumption. the clkm clock frequency settings for clkm_ctrl values 6 and 7 are not intended to directly clock the microcontroller. when using these clock rates, clkm is turned off immediately when entering sleep state. figure 4-15. sleep and wake-up initiated by asynchronous microcontroller timer clkm slp_tr 35 clkm clock cycles clkm off t tr2 async timer elapses (microcontroller) note: timing figure t tr2 refers to table 5-1. rx_on and rx_aack_on states for synchronous systems, where clkm is used as a microcontroller clock source and the spi master clock (sclk) is directly derived from clkm, the AT86RF212 supports an additional power-down mode for receive operating states (rx_on and rx_aack_on).
24 8168b-mcu wireless-02/09 AT86RF212 if an incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames. this can be achieved by a rising edge on pin slp_tr that turns off the clkm. then the radio transceiver state changes from rx_on or rx_aack_on (extended operating mode) to rx_on_noclk or rx_aack_on_noclk respectively. in case that a frame is received (e.g. indicated by an irq_2 (rx_start) interrupt) the clock output clkm is automatically switched on again. this scenario is shown in figure 4-16. in rx_on state, t he clock at pin 17 (clkm) is switched off after 35 clock cycles when setting the pin slp_tr = h. the clkm clock frequency settings for clkm_ctrl values 6 and 7 are not intended to directly clock the microcontroller. when using these clock rates, clkm is turned off immediately when entering rx_on_noclk and rx_aack_on_noclk respectively. in states rx_(aack)_on_noclk and rx_(aa ck)_on, the radio transceiver current consumptions are equivalent. however, the rx_(aack)_on_noclk current consumption is reduced by the current required for driving pin 17 (clkm). figure 4-16. wake-up initiated by radio transceiver interrupt clkm slp_tr 35 clkm clock cycles clkm off irq typ. 5 s radio transceiver irq issued 4.7 interrupt logic 4.7.1 overview the at 86rf212 supports 8 interrupt requests as listed in table 4-15. each interrupt is enabl ed by setting the corresponding bit in the interrupt mask register 0x0e (irq_mask). internally, eac h pending interrupt is stored in a separate bit of the interrupt status register. all interrupt ev ents are or-combined to a single external interrupt signal (irq, pin 24). if an interrupt is issued (pin irq = h), the microcontroller shall read the interrupt status register 0x0f (irq_status) to determine the source of the interrupt. a read access to this register clears the interrupt status register and thus the irq pin, too. interrupts are not cleared automatically wh en the event that caused them vanishes. exceptions are irq_0 (pll_lock) and irq_1 (pll_unlock) because the occurrence of one clears the other. the supported interrupts for the basic operating mode are summarized in table 4-15.
25 8168b-mcu wireless-02/09 AT86RF212 table 4-15. interrupt description in basic operating mode irq name description section irq_7 (bat_low) indicates a supply vo ltage below the programmed threshold. 7.6.4 irq_6 (trx_ur) indicates a frame buffer access violation. 7.4.3 irq_5 (ami) indicates address matching. 6.2 irq_4 (cca_ed_done) multi-functional interrupt: 1. awake_end: ? indicates radio transceiver reached trx_off state at the end of p_on ? trx_off and sleep ? trx_off state transition 2. cca_ed_done: ? indicates the end of a cca or ed measurement o 5.1.2.3 6.6.4 irq_3 (trx_end) rx: indicates the co mpletion of a frame reception. tx: indicates the completion of a frame transmission. 5.1.3 irq_2 (rx_start) indicates the start of a psdu reception. the trx_state changes to busy_rx, the phr is valid to be read from frame buffer. 5.1.3 irq_1 (pll_unlock) indicates pll unlock. if the radio transceiv er is in busy_tx / busy_tx_aret state, the pa is turned off immediately. 7.8.5 irq_0 (pll_lock) indicates pll lock. 7.8.5 the interrupt irq_4 has two meanings, depending on the current radio transceiver state, refer to register 0x01 (trx_status). after p_on, sleep, or reset, the radi o transceiver issues an interrupt irq_4 (awake_end) when it enters state trx_off. the second meaning is only valid for receiv e states. if the microcontroller initiates an ed or cca measurement, the completion of t he measurement is indicated by interrupt irq_4 (cca_ed_done), refer to sections 6.5.4 and 6.6.4 for details. after p_on or reset all interrupts are disabl ed. during radio transceiver initialization it is recommended to enable ir q_4 (awake_end) to be not ified once the trx_off state is entered. note that awake_end inte rrupt can usually not be seen when the transceiver enters trx_off state after r eset, because register 0x0e (irq_mask) is reset to mask all interrupts. in this case, state trx_off is normally entered before the microcontroller could modify the register. the interrupt handling in extended oper ating mode is described in section 5.2.5. if regis ter bit irq_mask_mode (register 0x04, trx_ctrl_1) is set, an interrupt event can be read from irq_status register even if the interrupt itself is masked, refer to figure 4-18. however, in that case no ti mi ng information for this interrupt is provided. the irq pin polarity can be configured with register bit irq_polarity (register 0x04, trx_ctrl_1). the default behavior is active high, which means that pin irq = h issues an interrupt request. if ?frame buffer empty indicator? is enabled during frame buffer read access the irq pin has an alternative functionality, refer to section 9.6 for details. a solution to monitor the irq_status regist er (without clearing it) is described in section 4.4.
26 8168b-mcu wireless-02/09 AT86RF212 4.7.2 register description regis ter 0x0e (irq_mask) : the irq_mask register is used to enable or di sable individual interrupts. an interrupt is enabled if the corresponding bit is set to 1. all interrupts are disabled after power up sequence (p_on state) or reset (reset state). table 4-16. register 0x0e (irq_mask) bit 7 6 5 4 name mask_bat_low mask_trx_ur mask_ami mask_ cca_ed_done read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name mask_trx_end mask_rx_start mask_ pll_unlock mask_pll_lock read/write r/w r/w r/w r/w reset value 0 0 0 0 if an interrupt is enabled, it is recommended to read the interrupt status register 0x0f (irq_status) first to clear the history. register 0x0f (irq_status) : the irq_status register contains the status of the pending interrupt requests. table 4-17. register 0x0f (irq_status) bit 7 6 5 4 name bat_low trx_ur ami cca_ed_done read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name trx_end rx_start pll_unlock pll_lock read/write r r r r reset value 0 0 0 0 by reading the register after an interrupt is signaled at pin 24 (irq) the source of the issued interrupt can be identified. a read access to this register resets all interrupt bits, and so clears the irq_status register. if register bit irq_mask_mode (register 0x04, trx_ctrl_1) is set, an interrupt event can be read from irq_status register even if the interrupt itself is masked, refer to figure 4-18. however in that case no timi ng information for this interrupt is provided. if register bit irq_mask_mode is set, it is recommended to read the interrupt status register 0x0f (irq_status) first to clear the history.
27 8168b-mcu wireless-02/09 AT86RF212 register 0x04 (trx_ctrl_1) : the trx_ctrl_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. table 4-18. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode irq_mask_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en rx/tx indicator, refer to section 9.4.3. ? bit 6 ? irq _2_ext_en the timing of a received frame can be deter mined by a separate pin. if register bit irq_2_ext_en is set to 1, the reception of a phr field is directly issued on pin 10 (dig2), similar to interrupt irq_2 (rx_start). note that this pin is also active even if the corresponding interrupt event irq_2 (rx_start) mask bit in register 0x0e (irq_mask) is set to 0. the pin rema ins at high level until the end of the frame receive procedure. for further details refer to section 9.5. ? bit 5 ? tx_ auto_crc_on refer to section 6.3.5. ? bit 4 ? rx_ bl_ctrl refer to section 9.6.2. ? bit 3:2 ? spi_cm d_mode refer to section 4.4.1. ? bit 1 ? irq _mask_mode the AT86RF212 supports polling of interrupt ev ents. interrupt polling can be enabled by register bit irq_mask_mode. even if an interrupt request is masked by the corresponding bit in register 0x0e (irq_m ask), the event is indicated in register 0x0f (irq_status).
28 8168b-mcu wireless-02/09 AT86RF212 table 4-19. irq mask configuration irq_mask value irq_ma sk_mode description 0 0 irq is suppressed entirely and none of interrupt causes are shown in register irq_status. 0 1 irq is suppressed entirely but all interrupt causes are shown in register irq_status. 0 0 all enabled interrupts are signaled on pin irq and are also shown in register irq_status. 0 1 all enabled interrupts are signaled on pin irq and all interrupt causes are shown in register irq_status. figure 4-17. irq_mask_mode = 0 irq_mask (register 0x0e) irq_status (register 0x0f) or irq interrupt sources . . . figure 4-18. irq_mask_mode = 1 or irq interrupt sources irq_mask (register 0x0e) . . . irq_status (register 0x0f) x bit 0 ? irq_polarity the default polarity of the irq pin is active high. the polarity can be configured to active low via register bit irq_polarity, see table 4-20. table 4-20. config uration of pin 24 (irq) register bit value description 0 pin irq high active irq_polarity 1 pin irq low active this setting does not affect the polarity of the frame buffer empty indicator, refer to section 9.6. the frame buffer empty indicator is always active high.
29 8168b-mcu wireless-02/09 AT86RF212 5 operating modes 5.1 basic operating mode this section summarizes all states to provi de the basic functionality of the AT86RF212, such as receiving and transmitting frames, the power up sequence and sleep. the basic operating mode is designed for ieee 802.15.4 and ism applications; the corresponding radio transceiver states are shown in figure 5-1. figure 5-1. basi c operating mode state diagram (for timing refer to table 5-1) 2 t r x _ o f f s l p _t r = h s l p _t r = l p l l _ o n rx_on pll_on trx_off (clock state) xosc=on pull=off r x _ o n p_on (power-on after evdd) xosc=on pull=on sleep (sleep state) xosc=off pull=off (all states except p_on) force_trx_off (all states except sleep) shr detected frame end frame end busy_tx (transmit state) pll_on (pll state) tx_start or t r x _o f f t r x _o f f 1 3 4 5 7 6 8 9 11 10 rx_on_noclk (rx listen state) clkm=off slp _tr = h sl p _ t r = l shr detected 12 13 /rst = h force_pll_on (all states except sleep, p_on, trx_off, rx_on_noclk) 14 slp_tr = h legend: blue : spi write to register trx_state (0x02) red : control signals via ic pin green : event basic operating mode states state transition number, see table 7-1 rx_on (rx listen state) busy_rx (receive state) reset (from all states) /rst = l x 5.1.1 state control the radio tra nsceiver states are controlled ei ther by writing commands to register bits trx_cmd (register 0x02, trx_state), or directly by two signal pins: pin 11 (slp_tr) and pin 8 (/rst). a succ essful state change can be verified by reading the radio transceiver status from register 0x01 (trx_status).
30 8168b-mcu wireless-02/09 AT86RF212 if trx_status = 0x1f (state_transitio n_in_progress) the AT86RF212 is in a state transition. do not try to initiate a further state change while the radio transceiver is in state_transition_in_progress. pin slp_tr is a multifunctional pin, refer to section 4.6. depending on the radio transceiver state, a rising edge of pin slp_tr causes the following state transitions: ? trx_off : sleep ? rx_on : rx_on_noclk ? pll_on : busy_tx whereas the falling edge of pin slp_tr causes the following state transitions: ? sleep : trx_off ? rx_on_noclk : rx_on pin 8 (/rst) causes a reset of all regist ers (register bits clkm_ctrl are shadowed, for details refer to section 7.7.4), and the content of the sr am it d eleted. it forces the radio transceiver into trx_off state. howeve r, if the device was in p_on state it remains in p_on state. for all states except sleep, the st ate change commands force_trx_off or trx_off lead to a transition into trx_off state. if the radio transceiver is in active receive or transmit states (busy_*), the command force_trx_off interrupts these active processes, and forces an immediate transition to trx_off. by contrast a trx_off command is stored until an active state (receiving or transmitting) has been finished. after that the transit ion to trx_off is performed. for a fast transition from receive or acti ve transmit states to pll_on state the command force_pll_on is provided. active processes are interrupted. in contrast to force_trx_off this command does not disable the pll and the analog voltage regulator avreg. it is not available in states sleep, reset, and all *_noclk states. the completion of each requested state chang e shall always be confirmed by reading the register bits trx_status (register 0x01, trx_status). 5.1.2 description 5.1.2.1 p_on ? po wer-on after evdd when the external supply voltage (evdd) is applied first to the AT86RF212 the radio transceiver goes into p_on state performing an on-chip re set. the crystal oscillator is activated and the default 1 mhz master clock is provided at pin 17 (clkm) after the crystal oscillator has stabilized. clkm can be used as a cl ock source to the microcontroller. the spi interface and digital voltage regulator are enabled. the on-chip power-on-reset sets all registers to their default values. a dedicated reset signal from the microcontroller at pin 8 (/rst) is not necessary, but recommended for hardware/software synchronization reasons. all digital inputs have pull-up or pull-down re sistors during p_on state, refer to section 2.2.2.2. this is necessary to support micr o controllers where gpio signals are floating after power on or reset. the input pull-up and pull-down resistors are disabled when the radio transceiver leaves p_on state. leavi ng p_on state, output s pins dig1/dig2 are internally connected to digital ground, wher eas pins dig3/dig4 are internally connected to analog ground, unless their configuration is changed. a reset at pin 8 (/rst) does not enable the pull-up or pull-down resistors.
31 8168b-mcu wireless-02/09 AT86RF212 prior to leaving p_on, the microcontroller must set the input pins to the default operating values: slp_tr = l, /rst = h and /sel = h. all interrupts are disabled by default. thus, in terrupts for state transition control are to be enabled first, e.g. enable irq_4 (awake_en d) to indicate a state transition to trx_off state. in p_on state a first acce ss to the radio transceiver registers is possible after a default 1 mhz master clock is provided at pin 17 (clkm), refer to t tr1 in table 5-1. once the supply voltage has stabilized and the crystal oscillator has settled (see section 10.5, parameter t xtal ), the interrupt mask for the awake_end should be set. a valid spi write access to register bits trx_cm d (register 0x02, trx_state) with the command trx_off or force_trx_off initiates a state change from p_on towards trx_off state, which is then indicate d by an awake_end interrupt if enabled. 5.1.2.2 sleep ? sleep state in sleep state, the entire radio transceiver is disabled. no circuitry is operating. the radio transceiver current consumption is redu ced to leakage current and the current of a low power voltage regulator (typ. 100 na), wh ich provides the supply voltage for the registers such that the contents of them remains valid. this state can only be entered from state trx_off, by setting slp_tr = h. if clkm is enabled, the sleep state is entered 35 clkm cycles after the rising edge at pin 11 (slp_tr). at that time clkm is turned off. if the clkm output is already turned off (bits clkm_ctrl = 0 in register 0x03), the sleep state is entered immediately. at clock rates of 250 khz and symbol clock rate (clkm_ctrl values 6 and 7, register 0x03, trx_ctrl_0), the main clock at pin 17 (clkm) is turned off immediately. setting slp_tr = l returns the radio transceiver back to the trx_off state. during sleep the register contents remains valid while the content of the frame buffer and the security engine (aes) are cleared. /rst = l in sleep state returns the radio transceiver to trx_o ff state and thereby sets all registers to their default values. exceptions are register bits clkm_ctrl (register 0x03, trx_ctrl_0). these register bits require a specific treatment, for details see section 7.7.4. 5.1.2.3 trx_o ff ? clock state in trx_off, the crystal oscillator is runni ng and the master clock is available at pin 17 (clkm). the spi interface and digital voltage regulator are enabled, thus the radio transceiver registers, the frame buffer and security engine (aes) are accessible (see sections 7.4 and 9.1). in contrast to p_on state, pull-up and pull-down resistors are disabled. note that the analog front-end is disabled during trx_off. if trx_off_avdd_en (register 0x0c, trx_ctrl_2) is set, the analog voltage regulator is turned on, enabling faster switch to any transmit/receive state. entering the trx_off state from p_on, sleep, or reset state, the state change is indicated by interrupt irq_4 (awake_end) if enabled.
32 8168b-mcu wireless-02/09 AT86RF212 5.1.2.4 pll_on ? pll state entering the pll_on state from trx_off st ate enables the analog voltage regulator (avreg) first, unless the avreg is al ready switched on (register 0x0c, trx_off_avdd_en). after the voltage regulator has been settled (see table 5-2), the pll frequ ency synthesizer is enabled. when the pll has been settled at the receive frequency to a channel defined by regi ster bits channel (register 0x08, phy_cc_cca), cc_number (r egister 0x013, cc_ctrl_0), and cc_band (register 0x014, cc_ctrl_1), a su ccessful pll lock is indicat ed by issuing an interrupt irq_0 (pll_lock). after the rx_on command is issued in p ll_on state, register bits trx_status (register 0x01, trx_status) immediately i ndicate the radio being in rx_on state. however, frame reception can only start, once the pll has locked. the pll_on state corr esponds to the tx_on state in ieee 802.15.4. 5.1.2.5 rx_on and busy_rx ? rx listen and receive state the AT86RF212 receive mode is internally separated into rx_on state and busy_rx state. there is no difference between thes e states with respect to the analog radio transceiver circuitry, which is always turned on. in both states the receiver and the pll frequency synthesizer are enabled. during rx_on state the receiver listens fo r incoming frames. after detecting a valid synchronization header (shr ), the AT86RF212 automatically enters the busy_rx state. the reception of a non-zero phr field generates an irq_2 (rx_start), if enabled. during psdu reception the frame data are stored continuously in the frame buffer until the last byte was received. the completion of the frame reception is indicated by an interrupt irq_3 (trx_end) and the radio tran sceiver returns the state rx_on. at the same time the register bit rx_crc_valid (register 0x06, phy_rssi) is updated with the result of the fcs check (see section 6.3). re ceived frames are passed to the address match filter, refer to section 6.2. if the content of the mac addressing fi elds (refer to ieee 802.15.4 section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the addressing mode, an address match interrupt ir q_5 (ami) is issued, refer to 4.7. the expected address val ues are to be stored in register s 0x20 ? 0x2b (short address, pan id and ieee address). frame filtering is available in basic and extended operating mode, refer to section 6.2. leaving state rx_on is only possible by writ ing a state change command to register bits trx_cmd in register 0x02 (trx_state). 5.1.2.6 rx_on_noclk ? rx listen state without clkm if the radio transceiver is listening for an incoming frame and the microcontroller is not running an application, the mi crocontroller may be powered down to decrease the total system power consumption. this specific power-down scenario for systems running in clock synchronous mode (see section 4), is supported by the AT86RF212 using the state rx_ on_noclk. this state can only be entered by setting pin 11 (slp_tr) = h while the radio transceiver is in rx_on state, refer to chapter 0. pin 17 (clkm) is disabled 35 clock cycle s after the rising edge at the slp_tr pin, see figure 4-16. this allows the microcontroll er to complete its power-down sequence.
33 8168b-mcu wireless-02/09 AT86RF212 note that for clkm clock rates 250 khz and symbol clock rates (clkm_ctrl values 6 and 7; register 0x03, trx_ctrl_0) the mast er clock signal clkm is switched off immediately after rising edge of slp_tr. the reception of a frame shall be indicat ed to the microcontroller by an interrupt indicating the receive status. clkm is turned on again, and the radio transceiver enters the busy_rx state (see section 4.6 and figure 4-16). when using rx_on_noclk, it is esse ntial to enable at least one interrupt request indicating the reception status. after the receive transaction has been comp leted, the radio transceiver enters the rx_on state. the radio transceiver only reenters the rx_on_noclk state, when the next rising edge of pin slp_tr pin occurs. if the AT86RF212 is in the rx_on_noclk state, and pin slp_tr is reset to logic low, it enters the rx_on state, and it starts to supply clock on the clkm pin again. a reset in state rx_on_noclk further requires to reset pin slp_tr to logic low, otherwise the radio transceiver enters directly the sleep state. note ? a reset in state rx_on_noclk further requires to reset pin slp_tr to logic low, otherwise the radio transceiver enters directly the sleep state. 5.1.2.7 busy_tx ? transmit state a transmission can only be initiated in stat e pll_on. there are two ways to start a transmission: ? rising edge of pin 11 (slp_tr) ? tx_start command written to register bits trx_cmd (register 0x02, trx_state). either of these forces the radio tr ansceiver into the busy_tx state. during the transition to busy_tx state, t he pll frequency shifts to the transmit frequency. the actual transmission of the fi rst data chip of the shr starts after 1 symbol period (refer to section 7.1.3) in order to allow pll settling and pa ramp-up, see figure 5-6. after transmission of the shr, t he frame buffer content is transmitted. in case the phr indicates a frame length of zero, the transmission is aborted immediately after the phr field. after the frame transmission has been comple ted, the AT86RF212 automatically turns off the power amplifier, generates an ir q_3 (trx_end) interrupt and returns into pll_on state. 5.1.2.8 reset state the reset state is used to set back the stat e machine and to reset all registers of the AT86RF212 to their default values, excepti on are register bits clkm_ctrl (register 0x03, trx_ctrl_0). these register bits re quire a specific treatment, for details see section 7.7.4. a res et forces the radio transceiver into trx_off state. if, however, the device is in p_on state it remains in p_on state. a reset is initiated with pin /rst = l and the state returns after setting /rst = h. the reset pulse should have a minimum length as specified in section 10.4, parameter 10.4.13.
34 8168b-mcu wireless-02/09 AT86RF212 during reset, the microcontroller has to set the radio transceiver control pins slp_tr and /sel to their default values. an overview of the register reset values is provided in table 11-2. 5.1.3 interrupt handling all interrupts provid ed by the AT86RF212 (see table 4-15) are supported in basic operating mo de. for example, interrupts are provided to obse rve the status of radio transceiver rx and tx operations. when being in receive mode, irq_2 (rx_star t) indicates the detection of a non-zero phr first, irq_5 (ami) an address match and irq_3 (trx_end) the completion of the frame reception. during transmission irq_3 (trx_end) i ndicates the completion of the frame transmission. figure 5-2 shows an example for a transmit/receive tran saction between two devices and the related interrupt events in basic op erating mode. device 1 transmits a frame containing a mac header, mac payload, and a valid fcs. the end of the frame transmission is indicated by irq_3 (trx_end). the frame is received by device 2. interrupt irq_2 (rx_start) indicates the detection of a valid phr field, and irq_ 3 (trx_end) the completion of the frame reception. if the frame passes the frame filt er, refer to 6.2, an address match interrupt irq_5 (ami) is issued after the reception of the mac header (mhr). processing delay t irq is a typical value, refer to section 10.4. figure 5-2. timing of rx_start, ami, and trx_e nd interrupts in basic operating mode for o-qpsk 250 kbit/s mode 128 160 192 0192+( m+n+2 )*32 time [s] rx (device 2) irq_2 (rx_start) t irq rx_on rx_on irq trx_state interrupt latency trx_end irq_5 (ami) t irq t irq busy_rx irq_3 (trx_end) tx (device1) pll_on busy_tx pll_on irq slp_tr trx_state processing delay frame on air preamble sfd phr msdu 41 1 m number of octets frame content mhr fcs 2 t tr10 -t tr10 n
35 8168b-mcu wireless-02/09 AT86RF212 5.1.4 timing the follo wing paragraphs depict state transi tions and their timing properties. timings are explained in table 5-1 and section 10.4. 5.1.4.1 powe r-on procedure the power-on procedure during p_on state is shown in figure 5-3. figure 5-3. powe r-on procedure during p_on state 0 event state evdd on p_on block xosc, dvreg 100 clkm on 400 time [s] time t tr1 when the external supply voltage (evdd) is supplied to the AT86RF212, the radio transceiver enables the crystal oscillato r (xosc) and the internal 1.8 v voltage regulator for the digital domain (dvreg). after t tr1 , the master clock signal is available at pin 17 (clkm) at default rate of 1 mhz. if clkm is available, the spi has already been enabled and can be used to control the transceiver. 5.1.4.2 wake-up procedure the wake-up procedure from sleep state is shown in figure 5-4. figure 5-4. wak e-up procedure from sleep state 0 event state block 100 clkm on 400 time [s] time t tr2 trx_off irq_4 (awake_end) slp_tr = l sleep 200 xosc, dvreg xosc, dvreg ftn the radio transceiver?s sleep state is left by releasing pin slp_tr to logic low. this restarts the xosc and dvreg. after t tr2 , the radio transceiver enters trx_off state. the internal clock signal is available and provided to pin 17 (clkm), if enabled. this procedure is similar to power-on, how ever, the radio transceiver automatically ends in trx_off state. during this the f ilter-tuning network (ftn) calibration is performed. entering trx_off state is signaled by irq_4 (awake_end), if this interrupt was enabled by the appr opriate mask register bit. 5.1.4.3 state change from trx_off to pll_on / rx_on the transition from trx_off to pll_on or rx_on mode and further to rx_on or pll_on is shown in figure 5-5.
36 8168b-mcu wireless-02/09 AT86RF212 figure 5-5. transition from trx_off to pll_on/rx_on state and further to rx_on/pll_on 0 event state block 100 time [s] time t tr4 / t tr6 irq_0 (pll_lock) trx_off avreg command pll_on / rx_on pll pll_on / rx_on rx_on / pll_on t tr8 /t tr9 rx_on / pll_on note: if trx_cmd = rx_on in trx_off state rx _on state is entered immediately, even if the pll has not settled. in trx_off state, entering the commands pll_on or rx_on initiates a ramp-up sequence of the internal 1.8 v voltage regulator for the analog domain (avreg). rx_on state can be entered any time from pl l_on state, regardless whether the pll has already locked, which is indicated by irq_0 (pll_lock). likewise, pll_on state can be entered any time from rx_on state. when trx_off_avdd_en (register 0x0c, trx_ctrl_2) is already set in trx_off state, the analog voltage regulator is turn ed on immediately and the ramp up sequence to pll_on or rx_on can be accelerated. 5.1.4.4 state change from pll_on via busy_tx to rx_on states the transition from pll_on to busy_tx state and subsequently to rx_on state is shown in figure 5-6. figure 5-6. pll_on to busy_tx to rx_on timi ng for o-qpsk 250 kbit/s mode time [s] 0x 16 x + 32 time t tr11 t tr10 state block pll_on rx_on busy_tx event slp_tr=h or trx_cmd =tx_start pll tx rx trx_cmd=rx_on irq_3 (trx_end) starting from pll_on, it is further assum ed that the pll has already been locked. a transmission is initiated either by a risi ng edge of pin 11 (slp_tr) or by command tx_start. the pll settles to the transmit frequency and the pa is enabled. after the duration of t tr10 (1 symbol period), the AT86RF212 changes into busy_tx state, transmitting the internally gener ated shr and the psdu data of the frame buffer.
37 8168b-mcu wireless-02/09 AT86RF212 after completing the frame transmission, indicated by irq_3 (trx_end), the pll settles back to the receive frequency within t tr11 and returns to state pll_on. if during busy_tx the radio transmitter is requ ested to change to a receive state, it automatically proceeds to state rx_on upon completion of the transmission, refer to figure 5-6. 5.1.4.5 re set procedure the radio transceiver reset procedure is shown in figure 5-7. figure 5-7. re set procedure x event state block time [s] pin /rst trx_off x + 40 [irq_4 (awake_end) ] 0 any time t 10 t tr13 t 11 x + 10 ftn undefined /rst = l sets all registers to their defaul t values. exceptions are register bits clkm_ctrl (register 0x03, trx_ctrl_0), refer to section 7.7.4. after rele asing the reset pin (/rst = h) the wake-up sequence including an ftn calibration cycle is performed, refer to section 7.9. after that the trx_off state is entere d. figure 5-7 illustrates the reset procedure once p_on state was left and the radio transceive r was not in sleep state. the reset procedure is identical for all orig inating radio transceiver states except of state p_on and sleep state. instead, t he procedures desc ribed in section 5.1.2.1 and 5.1.2.2 must be followed to enter the t rx_off state. if the radio transceiver was in sleep stat e, the xosc and dvreg are enabled before entering trx_off state. notes ? the reset impulse should have a minimum length t 10 as specified in section 10.4, see para meter 10.4.13. ? an access to the device should not occur earlier than t 11 after releasin g the pin /rst; refer to section 10.4, parameter 10.4.14. ? a reset overrides an spi command that might be queued. 5.1.4.6 state transition timing summary transition timings are listed in table 5-1 and do not include spi access time if not otherwise sta ted. see measurement setup in figure 3-1.
38 8168b-mcu wireless-02/09 AT86RF212 table 5-1. state transition timing symbol transition time, typ. comments t tr1 p_on ? until clkm available 330 s depends on crystal oscillator setup (siward a207-011, c l = 10 pf) and external capacitor at dvdd (1 f nom.) t tr2 sleep ? trx_off 380 s depends on crystal oscillator setup (siward a207-011, c l = 10 pf) and external capacitor at dvdd (1 f nom.) trx_off state indicated by irq_4 (awake_end) t tr3 trx_off ? sleep 35 cycles of clkm for f clkm > 250 khz t tr4 trx_off ? pll_on 110 s depends on external capacitor at avdd (1 f nom.); register bit trx_off_avdd_en (register 0x0c, trx_ctrl_2) is not set t tr5 pll_on ? trx_off 1 s t tr6 trx_off ? rx_on 110 s depends on external capacitor at avdd (1 f nom.); register bit trx_off_avdd_en (register 0x0c, trx_ctrl_2) is not set t tr7 rx_on ? trx_off 1 s t tr8 pll_on ? rx_on 1 s t tr9 rx_on ? pll_on 1 s transition time is also valid for tx_aret_on, rx_aack_on t tr10 pll_on ? busy_tx 1 symbol period when asserting pin 11 (slp_tr) or trx_cmd = tx_start first symbol transmission is delayed by 1 symbol period (pll settling and pa ramp up), refer to section 7.1.3. t tr11 busy_tx ? pll_on 32 s pll settling time t tr12 all states ? trx_off 1 s using trx_cmd = force_trx_off (see register 0x02, trx_state); not valid for sleep state t tr13 reset ? trx_off 26 s not valid for p_on or sleep state t tr14 various states ? pll_on 1 s using trx_cmd = force_pll_on (see register 0x02, trx_state); not valid for sleep, p_on, reset, trx_off, and *_no_clk the state transition timing is calculated based on the timing of the individual blocks shown in figure 5-3 to figure 5-7. the worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations, see table 5-2. table 5-2. analog block ini tialization and settling times symbol block time, typ. time, max. comments t tr15 xosc 330 s 1000 s leaving sleep state, depends on crystal q factor and load capacitor t tr16 ftn 25 s filter tuning time t tr17 dvreg 60 s 1000 s depends on external bypass capacitor at dvdd (cb3 = 1 f nom., 10 f worst case), and on evdd voltage t tr18 avreg 60 s 1000 s depends on external bypass capacitor at avdd (cb1 = 1 f nom., 10 f worst case) , and on evdd voltage t tr19 pll, initial 96 s 276 s pll settling time trx_off > pll_on, including 60 s avreg settling time t tr20 pll, settling 11 s 42 s duration of channel switch within frequency band t tr21 pll, cf cal. 8 s 270 s pll center frequency calibration, refer to section 7.8.4 t tr22 pll, dcu cal. 10 s pll dcu calibration, refer to section 7.8.4 t tr23 pll, rx ? tx 16 s pll settling time rx ? tx
39 8168b-mcu wireless-02/09 AT86RF212 symbol block time, typ. time, max. comments t tr24 pll, tx ? rx 32 s pll settling time tx ? rx t tr25 rssi bpsk-20: 32 s bpsk-40: 24 s o-qpsk: 8 s rssi update period in receive states, refer to section 6.4.2 t tr26 ed 8 symbol periods ed measurement period, refer to section 6.5 different timin g with high data rate modes, see sections 6.5.5 and 7.1.4.3 t tr28 cca 8 symbol periods cca measurement period, refer to section 6.6.2 t tr29 random value 1 s random value update period, refer to section 9.2.1 5.1.5 register description regis ter 0x01 (trx_status) : a read access to trx_status register si gnals the current radio transceiver state. a state change is initiated by writing a state transition command to register bits trx_cmd (register 0x02, trx_state). alternat ively, a state transition can be initiated by the rising edge of pin 11 (slp _tr) in the appropriate state. this register is used for basic and ex tended operating mode, refer to section 5.2. table 5-3. registe r 0x01 (trx_status) bit 7 6 5 4 name cca_done cca_status reserved trx_status[4] read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name trx_status[3] trx_status[2] trx_status[1] trx_status[0] read/write r r r r reset value 0 0 0 0 ? bit 7 ? cca_done refer to section 6.6 ? bit 6 ? c ca_status refer to section 6.6 ? bit 5 ? reser ved ? bit 4:0 ? trx_status the register bits trx_status signal t he current radio transceiver status. if the requested state transition is not co mpleted yet, the trx_status returns state_transition_in_progress. do not tr y to initiate a further state change while the radio transceiver is in state_ transition_in_progr ess. state transition timings are defined in table 5-1. table 5-4. radio tran sceiver status, register bits trx_status register bits value state description 0x00 p_on trx_status 0x01 busy_rx
40 8168b-mcu wireless-02/09 AT86RF212 register bits value state description 0x02 busy_tx 0x06 rx_on 0x08 trx_off (clk mode) 0x09 pll_on (tx_on) 0x0f (3) sleep 0x11 (1) busy_rx_aack 0x12 (1) busy_tx_aret 0x16 (1) rx_aack_on 0x19 (1) tx_aret_on 0x1c rx_on_noclk 0x1d (1) rx_aack_on_noclk 0x1e (1) busy_rx_aack_noclk 0x1f (2) state_transition_in_progress all other values are reserved notes: 1. extended operating mode only, refer to section 5.2. 2. do not try to initiate a further stat e change while the radio transceiver is in state_transition_in_progress state. 3. in sleep state regi ster not accessible. register 0x02 (trx_state) : radio transceiver state changes can be initiat ed by writing register bits trx_cmd. this register is used for basic and ext ended operating mode, refer to section 5.2. table 5-5. registe r 0x02 (trx_state) bit 7 6 5 4 name trac_status trac_status trac_status trx_cmd[4] read/write r r r r/w reset value 0 0 0 0 bit 3 2 1 0 name trx_cmd[3] trx_cmd[2] trx_cmd[1] trx_cmd[0] read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:5 ? trac_status refer to section 5.2.6. ? bit 4:0 ? trx_cm d a write access to register bits trx_cmd in itiates a radio transceiver state transition. table 5-6. state control command, register bits trx_cmd register bits value state transition towards 0x00 nop 0x02 tx_start trx_cmd 0x03 force_trx_off
41 8168b-mcu wireless-02/09 AT86RF212 register bits value state transition towards 0x04 (1) force_pll_on 0x06 rx_on 0x08 trx_off (clk mode) 0x09 pll_on (tx_on) 0x16 (2) rx_aack_on 0x19 (2) tx_aret_on all other values are reserved and mapped to nop notes: 1. force_pll_on is not valid for states sleep, reset, and all *_noclk states, as well as state_transition_in_progress towards these states. 2. extended operating mode only, refers to section 5.2.6. 5.2 extended operating mode the extended operating mode is a hard ware mac accelerator and goes beyond the basic radio transceiver functionality provi ded by the basic operating mode. it handles time critical mac tasks, requested by t he ieee 802.15.4-2003/2006 standard, such as automatic acknowledgement, automatic csma-c a, and retransmission. this results in a more efficient ieee 802.15.4-2003/2006 software mac implementation including reduced code size and may allow the use of a smaller microcontroller. the extended operating mode is desi gned to support i eee 802.15.4-2003/2006 standard compliant frames and comprises the following procedures: automatic acknowledgement (rx_aack transaction) divides into the tasks: ? frame reception and automatic fcs check ? configurable addressing fields check ? interrupt indicating address match ? interrupt indicating frame reception, if it passes frame filtering and fcs check ? automatic acknowledgment (ack) frame transmission, if applicable ? support of slotted acknowledgment using slp_tr pin (used for beacon-enabled operation) automatic csma-ca and retransmission (tx_ aret transaction) divides into the tasks: ? csma-ca including automatic cca retry and random backoff ? frame transmission and automatic fcs field generation ? reception of ack frame (if ack was requested) ? automatic retry of transmissions if ack was expected but not received or accepted ? interrupt signaling with transaction status an AT86RF212 state diagram including the extended operating mode states is shown in figure 5-8. yellow marked states represent the basic operating mode; blue marked states represent the extended operating mode.
42 8168b-mcu wireless-02/09 AT86RF212 figure 5-8. extended operating mode state diagram 2 t r x _ o f f s l p _ t r = h legend: blue : spi write to register trx_state (0x02) red : control signals via ic pin green : event basic operating mode states extended operating mode states s l p _ t r = l p l l _ o n rx_on pll_on trx_off (clock state) xosc=on pull=off r x _ o n p_on (power-on after evdd) xosc=on pull=on sleep (sleep state) xosc=off pull=off (all modes except p_on) force_trx_off (all modes except sleep) frame end frame end busy_tx (transmit state) rx_on (rx listen state) busy_rx (receive state) t r x _ o f f t r x _ o f f 1 3 4 5 7 6 8 9 11 10 rx_on_noclk (rx listen state) clkm=off s l p _ t r =h slp _ tr =l busy_rx_aack busy_tx_aret shr detected trans- action finished tx_aret_on pll_on slp_tr=h or tx_start frame end p l l _ o n r x _ a a c k _ o n rx_aack_ on_noclk busy_rx_ aack_noclk frame rejected frame accepted t x _ are t _ o n r x _ a a c k _ o n from trx_off from trx_off slp_tr=h slp_tr=l /rst = h 12 13 force_pll_on 14 shr detected slp_tr=h or tx_start shr detected shr detected tx_aret_on rx_aack_on clkm=off clkm=off pll_on (pll state) see notes reset (from all states) /rst = l
43 8168b-mcu wireless-02/09 AT86RF212 5.2.1 state control the extende d operating modes rx_aack and tx_aret are controlled via register bits trx_cmd (register 0x02, trx_state) , which receives the state transition commands. the corresponding states, rx_aack_on and tx_aret_on, respectively, are to be entered from stat es trx_off or pll_on as illustrated by figure 5-8. the success of the state cha nge shall be confirmed by reading register 0x01 (trx_status). rx_aack - receive with automatic ack a state transition to rx_aack_on from pll_o n or trx_off is initiated by writing the command rx_aack_on to register bits trx_cmd (register 0x 02, trx_state). on success reading register 0x01 (trx_status) returns rx_aack_on or busy_rx_aack. the latter one is returned if a frame is currently about being received. the rx_aack extended operating mode is terminated by writing command pll_on to the register bits trx_cmd. if the AT86RF212 is within a frame receive or acknowledgment procedure (busy_rx_aack) the state change is executed after finish. alternatively, the commands fo rce_trx_off or forc e_pll_on can be used to cancel the rx_aack transaction and change into transceiver state trx_off or pll_on, respectively. tx_aret - transmit with automatic retry and csma-ca retry similarly, a state transition to tx_aret_on from pll_on or trx_off is initiated by writing command tx_aret_on to register bits trx_cmd (register 0x02, trx_state). the radio transceiver is in the tx_aret_on state when register 0x01 (trx_status) returns tx_aret_on. the tx _aret transaction is actually started with a rising edge of pin 11 (slp_tr) or by writing the command tx_start to register bits trx_cmd. the tx_aret extended operating mode is terminated by writing the command pll_on to the register bits trx_cmd. if the AT86RF212 is within a csma-ca, a frame-transmit or an acknowledgment proc edure (busy_tx_aret) the state change is executed after finish. alternatively, the command force_pll_on can be used to instantly terminate the tx _aret transaction and cha nge into transceiver state pll_on. note ? a state change request from trx_off to rx_aack_on or tx_aret_on internally passes the state pll_on to init iate the radio transceiver front end. thus the readiness to receive or transmit data is delayed accordingly (see table 5-1). in that case it is recomme nded to use inte rrupt irq_0 (pll_lock) as an indicator. 5.2.2 configuration as the usage of the extended operating mode is based on basic operating mode functionality only features beyond the basic radio transceiver functionality are described in the following sections. for details of the basic operating mode refer to section 5.1. whe n using the rx_aack or tx_aret mode s, the following registers need to be configured.
44 8168b-mcu wireless-02/09 AT86RF212 rx_aack configuration steps: ? setup frame filter: registers 0x20 ? 0x2b o short address, pan id and ieee address ? configure acknowledgement generati on registers 0x2c, 0x2e o handling of frame version subfield o handling of pending data o automatic or slotted ack generation ? additional frame filtering properties register 0x17 o frame filter version control o characterize the device as pan coordinator, if required o promiscuous mode o handling of reserved frame types the configuration of frame filt er is described in section 6.2.1. the addresses for the address mat ch algorithm are to be stored in the appropriate address registers. additional control of the rx_aack mode is done with register 0x17 (xah_ctrl_1) and register 0x2e (csma_seed_1). configuration examples for different devi ce operating modes and handling of various frame types can be found in section 5.2.3.1. tx_aret co nfiguration steps: ? enable automatic fcs handling, if necessary register 0x04 ? configure csma-ca o max_frame_retries register 0x2c o max_csma_retries register 0x2c o csma_seed registers 0x2d, 0x2e o max_be, min_be register 0x2f ? configure cca (see section 6.6) max_fram e_retries (register 0x2c, xah _ctrl_0) defines the maximum number of frame retransmissions. the register bits max_csma_retries (r egister 0x2c) configure the maximum number of csma-ca retries after a busy channel is detected. the csma_seed_0 and csma_seed _1 register bits (regist ers 0x2d, 0x2e) define a random seed for the backoff time random-number generator in the AT86RF212. the register bits max_be and min_be (register 0x2f) define the maximum and minimum csma backoff exponent, respectively. 5.2.3 rx_aack_on ? receive with automatic ack the rx_aack extended operating mode handles reception and automatic acknowledgement of ieee 802.15.4 compliant frames. the general flow of the rx_aack algorithm is shown in figure 5-9. here the gray shaded area is t he standard flow of an rx_aac k transaction for ieee 802.15.4 compliant frames, refer to 5.2.3.2. all other procedures a re exceptions for specific operating modes or frame formats, refer to section 5.2.3.3.
45 8168b-mcu wireless-02/09 AT86RF212 in rx_aack_on state, the AT86RF212 liste ns for incoming frames. after detecting a non-zero phr, the AT86RF212 changes in to busy_rx_aack state and parses the frame content of the mac heade r (mhr), refer to section 6.1.2. if the conte nt of the mac addressing fiel ds of the received frame (refer to ieee 802.15.4 frame format, section 7.2.1) pa sses the frame filter, an address match interrupt irq_5 (ami) is issued. the refe rence address values are to be stored in registers 0x20 ? 0x2b (shor t address, pan id and ieee address). the frame filter operations are described in detail in section 6.2. gene rally, at nodes, configured as a normal device or pan coordinator, a frame is indicated by interrupt irq_3 (trx_end) if the frame passes the frame filter and the fcs is valid. the interrupt is issued afte r the completion of the frame reception. the microcontroller can then read the frame data. an excepti on applies if promiscuous mode is enabled; see section 5.2.3.2. in that case, an interrupt irq_3 is issued for all frames . during reception, the AT86RF212 parses bit 5 (ack request) of the frame control field of the received data or mac command fr ame to check if an acknowledgement (ack) response is expected. in that case and if t he frame matches the third level filtering rules (see ieee 802.15.4-2006, section 7.5.6.2) the radio transceiv er automatically generates and transmits an ack frame and proceeds back to rx_aack_on state. by default, the acknowledgment frame is transmitted aturnaroundtime (12 symbols, see ieee 802.15.4, section 6.4. 1) after the reception of t he last symbol of a data or mac command frame. optionally, for non- compliant networks this delay can be reduced to 2 symbols by register bit aac k_ack_time (register 0x2e, xah_ctrl_1). the content of the frame pending subfield of the ack response is set according to register bit aack_set_pd (register 0x2e, csma_seed_1). the sequence number is copied from the received frame accordingly. if the register bit aack_dis_ack (regi ster 0x2e, csma_seed_1) is set, no acknowledgement frame is sent, even if requested. for slotted operation, the start of the transmission of acknowledgement frames is controlled by pin 11 (slp_tr), refer to 5.2.3.5. the statu s of the rx_aack transaction is indicated by register subfield trac_status (register 0x02, trx_state). table 5-7 lists corresponding values. table 5-7. rx_aack interpretation of tr ac_status regis ter bits value name description 0 success the transaction has finished with success 2 success_wait_for_ack the transaction either waits aturnaroundtime symbols until the ack is transmitted or expects the rising edge on pin 11 (slp_tr) to start the transmission (slotted operation) 7 invalid default value, when rx_aack transaction is invoked note that generally the AT86RF212 phy modes as well as the extended feature set work independent from rx_aack extended operating mode.
46 8168b-mcu wireless-02/09 AT86RF212 figure 5-9. flow diagram of rx_aack reserved frames trx_state = rx_aack_on, transmit ack trx_state = rx_aack_on, trac_status = success n y note 2: additional conditions: - ack requested & - ack_dis_ack==0 & - frame_version<=aack_fvn_mode y y n y n n n y promiscuous mode note 1: address match, promiscuous mode and reserved frames: - a radio transceiver in promiscuous mode or configured to receive reserved frames handles received frames passing the third level of filtering - for details refer to the descritption of promiscuous mode and reserved frame types wait (aack_ack_time) wait (aack_ack_time) wait (pin 11, (slp_tr), rising edge) address match? fcs valid || aack_prom_mode ? ack requested ? (see note 2) trac_status = success_wait_for_ack no slotted operation ? receive psdu aack_prom_mode == 1 ? receive psdu fcf[2:0] > 3 ? aack_upld_res_ft == 1 ? fcs valid ? issue irq_3 (trx_end) issue irq_3 (trx_end) y y y issue irq_3 (trx_end) receive psdu issue irq_2 (rx_start) scan mhr detect shr ?ssue irq_5 (ami) trac_status = invalid trx_state = busy_rx_aack n n
47 8168b-mcu wireless-02/09 AT86RF212 5.2.3.1 configur ation registers overview rx_aack configuration as described bel ow shall be done prior to switching the AT86RF212 into state rx_aack_on, refer to 5.2.1. table 5-8 summarizes all register bits wh i ch affect the behavior of an rx_aack transaction. for frame filtering it is further required to setu p address registers to match to the expected address. table 5-8. overview of rx_aack configuration bits register address register bits register name description 0x20,0x21 0x22,0x23 0x24 ? 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 setup frame filter, see 6.2.1 0x0c 7 rx_safe_mode dynamic frame buffer protection, see 9.7 0x17 1 aack_prom_mode enable promiscuous mode 0x17 2 aack_ack_time modify auto acknowledge start time 0x17 4 aack_upld_res_ft enable reserved frame type reception, needed to receive non-standard compliant frames, see 5.2.3.3 0x17 5 aack_fltr_res_ft filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames, see 5.2.3.3 0x2c 0 slotted_operation if set, acknowledgment transmission has to be triggered by pin 11 (slp_tr), see 4.6 0x2e 3 aack_i_am_coord define device as pan coordinator, see 5.2.3.2 0x2e 4 aack_dis_ack disable generation of acknowledgment 0x2e 5 aack_set_pd signal pending data in frame control field (fcf) of acknowledgement 0x2e 7:6 aack_fvn_mode control the ack generation, depending on fcf frame version number the usage of the rx_aack configuration bi ts for various device types or operating modes is explained in the following sections . configuration bits not mentioned in the following two sections should be set to their reset values according to table 11-2. all registe rs mentioned in table 5-8 are described in section 5.2.6. 5.2.3.2 config uration of ieee compliant scenarios device not operating as a pan coordinator table 5-9 shows the rx_aack configuration regi sters, required to setup a typical ieee 802.15.4 compliant device.
48 8168b-mcu wireless-02/09 AT86RF212 table 5-9. configuration of ieee 802.15.4 devices register address register bits register name description 0x20,0x21 0x22,0x23 0x24 ? 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 setup frame filter, see section 6.2.1 0x0c 7 rx_safe_mode 0 : disable frame protection 1 : enable frame protection 0x2c 0 slotted_operation 0 : transceiver operates in unslotted mode. 1 : transceiver operates in slotted mode, see section 5.2.3.5. 0x2e 7:6 aack_fvn_mode controls the ack behavior, depending on fcf frame version number b00 : acknowledges only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames b01 : acknowledges only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2003/2006 b10 : acknowledges only frames with version number 0 or 1 or 2 b11 : acknowledges all frames, independent of the fcf frame version number notes ? the default value of the short address is 0xffff. thus, if no short address has been configured, only frames with either t he broadcast address or the ieee address are accepted by the frame filter. ? in the ieee 802.15.4-2003 standard, the fr ame version subfield does not yet exist, but is marked as reserved. according to th is standard, reserved fields have to be set to zero. at the same time, the i eee 802.15.4-2003 standar d requires ignoring reserved bits upon reception. thus, there is a contradiction in the standard which can be interpreted in two ways: 1. if a network should only allow access to nodes co mpliant to ieee 802.15.4-2003, then aack_fvn_mode should be set to 0. 2. if a device should acknowledge all fr ames independent of its frame version, aack_fvn_mode should be set to 3. however, this may result in conflicts with co-existing ieee 802.15.4-2006 st andard compliant networks. the same holds for pan coordinators, see below. pan coordinator table 5-10 shows the rx_aack configurati on registers, required to setup a pan coordinator device.
49 8168b-mcu wireless-02/09 AT86RF212 table 5-10. configuration of a pan coordinator register address register bits register name description 0x20,0x21 0x22,0x23 0x24 ? 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 setup frame filter, see section 6.2.1 0x0c 7 rx_safe_mode 0 : disable frame protection 1 : enable frame protection 0x2c 0 slotted_operation 0 : transceiver operates in unslotted mode. 1 : transceiver operates in slotted mode, see section 5.2.3.5. 0x2e 3 aack_i_am_coord 1 : device is pan coordinator 0x2e 5 aack_set_pd 0 : frame pending subfield is 0 in fcf 1 : frame pending subfield is 1 in fcf 0x2e 7:6 aack_fvn_mode controls the ack behavior depending on fcf frame version number b00 : acknowledges only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames b01 : acknowledges only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2003/2006 b10 : acknowledges only frames with version number 0 or 1 or 2 b11 : acknowledges all frames, independent of the fcf frame version number promiscuous mode or sniffer the promiscuous mode is described in ieee 802.15.4-2006, section 7.5.6.5. this mode is further illustrated in figure 5-9. according to ieee 802.15.4-2006 in promiscuous mode, th e mac sub layer shall pass received frames with correct fcs to the next higher layer without further processing. this implies that received frames should never be automatically acknowledged. in order to support sniffer application and pr omiscuous mode, only second level filter rules as defined by ieee 802.15. 4-2006, section 7.5.6.2, ar e applied to the received frame. table 5-11 shows the rx_aack configuration regi sters, required to setup a typical ieee 802.15.4 compliant device, whic h operates in promiscuous mode.
50 8168b-mcu wireless-02/09 AT86RF212 table 5-11. configuration of promiscuous mode register address register bits register name description 0x20,0x21 0x22,0x23 0x24 ? 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 each address shall be set: 0x00 0x17 1 aack_prom_mode 1 : enable promiscuous mode 0x2e 4 aack_dis_ack 1 : disable acknowledgment generation to signal the availability of frame data, an irq_3 (trx_end) is issued even if the fcs is invalid. thus, it is necessary to read register bit rx_crc_valid (register 0x06, phy_rssi) after irq_3 (trx_end) in order to verify the reception of a frame with a valid fcs. alternatively, bit 7 of byte rx _status can be evaluated, refer to section 4.3.2. if a devi ce, operating in promiscuous mode, received a frame with a valid fcs that furthermore passed the third level of filter ing (according to i eee 802.15.4-2006, section 7.5.6.2), an acknowledgement (ack) frame would be transmitted. but, according to the definition of the promiscuous mode a receiv ed frame shall not be acknowledged, even if requested. thus register bit aack_dis_ac k (register 0x2e, csma_seed_1) must be set to 1, to disable ack generation. in all receive modes, interrupt irq_5 (ami) is issued, if the received frame matches the node?s address according to the filter rules described in 6.2. promiscu ous mode could also be implemented using state rx_on (basic operating mode), refer to section 5.1. however, the rx_aack transactio n additionally enables extended functionality like automatic ackn owledgement and non-destructive frame filtering. 5.2.3.3 configuration of non ieee compliant scenarios reserved frame types in rx_aack mode, frames with reserv ed frame types, refer to section 6.1.2.2, table 6- 2, can also be handle d. this might be required when implementing proprietary, non- standard compliant protocols. the reception of reserved frame types is an extension of the AT86RF212 frame filter, see section 6.2. received frames are either handled like data frame s, or may be allowed to completely bypass the frame filter. the flow chart in figure 5-9 shows the corres po nding state machine. in addition to table 5-9 or table 5-10, the following table 5-12 shows rx_aack config uration registers, required to setu p a node to receive reserved frame types. table 5-12. rx_aack configuration to re ceive reserved frame types register address register bits register name description 0x17 4 aack_upld_res_ft 1 : enable reserved frame type reception 0x17 5 aack_fltr_res_ft filter reserved frame types like data frame type, see note below 0 : disable 1 : enable
51 8168b-mcu wireless-02/09 AT86RF212 there are two different options fo r handling reserved frame types. 1. aack_upld_res_ft = 1, aack_fltr_res_ft = 0: any non-corrupted frame with a reserved fram e type is indicated by the interrupt irq_3 (trx_end). no further frame filtering is applied on those frames. the interrupt irq_5 (ami) is never generated and no acknowledgment is sent. 2. aack_upld_res_ft = 1, aack_fltr_res_ft = 1: any frame with a reserved frame type is treated like an ieee 802.15.4 compliant data frame. this implies the generation of the interrupt irq_5 (ami) upon address matches. the irq_3 (trx_end) interrupt is only generated if the address matches and the frame is correct (fcs valid). then an acknowledgment is sent, if the ack request subfield of the received frame is set accordingly. short acknowledgment frame (ack) start timing register bit aack_ack_time (r egister 0x17, xah_ctrl_1), see table 5-13, defines the delay between the end of the frame recept ion and the start of the transmission of an acknowledgment frame. table 5-13. ack start timing for unslotted operation register address register bit register name description 0x17 2 aack_ack_time 0 : standard compliant acknowledgement delay of 12 symbol periods 1 : reduced acknowledgment delay of 2 symbol periods (bpsk-20, o-qpsk- {100,200,400}) or 3 symbol periods (bpsk-40, o-qpsk-{250,500,1000}). note that this feature can be used in all scenarios, independent of other configurations. however, shorter acknowledgment timing is especially useful when using high data rate modes to increase battery lifetime and to improve the overall data throughput; refer to section 7.1.4.3. in slotted o peration mode, the acknowledgment transmission is actually started by pin 11 (slp_tr). table 5-14 shows that the AT86RF212 enables the trigger pin with an approp riate delay. thus a transm ission cannot be started earlier. table 5-14. ack start timing for slotted operation register address register bit register name description 0x17 2 aack_ack_time 0 : acknowledgment frame transmission can be triggered after 6 symbol periods. 1 : acknowledgment frame transmission can be triggered after 3 symbol periods. 5.2.3.4 rx_aack_noclk ? rx_aack_on without clkm if the AT86RF212 is listening for an incoming frame and the microcontroller is not running an application, the microcontroller can be powered down to decrease the total system power consumption. this special po wer-down scenario for systems running in clock synchronous mode (see section 4.2) is supported by the AT86RF212 using the states rx_aack_on_noclk and busy_rx_aack_noclk, see figure 5-8. they
52 8168b-mcu wireless-02/09 AT86RF212 achieve the same functionality as the st ates rx_aack_on and busy_rx_aack with pin 17 (clkm) disabled. the rx_aack_noclk state is entered from rx_aack_on by a rising edge at pin 11 (slp_tr). the return to rx_aack_on state automatically results either from the reception of a valid frame, indicated by interrupt irq_3 (trx_end), or a falling edge on pin slp_tr. a received frame is considered valid if it pas ses frame filtering and has a correct fcs. if an ack was requested, the radio transceive r enters busy_rx_aack state and follows the procedure described in section 5.2.3. after the rx_aack transaction has been completed, the radio transceiver remains in rx_aack_on state. the AT86RF212 re- enters the rx_aack_on_noclk state only by the next rising edge on pin 11 (slp_tr). the timing and behavior when clkm is di sabled or enabled are described in section 4.6. note that rx _aack_noclk is not available for slotted operation mode (see 5.2.3.5). 5.2.3.5 slotted operation ? slotted ackn owledgement in networks using slotted operation the star t of the acknowledgment frame, and thus the exact timing, must be provided by the microc ontroller. exact timing requirements for the transmission of acknowledgments in beacon-enabled networks are explained in ieee 802.15.4-2006, sect ion 7.5.6.4.2. in conjunction with the microcontroller the AT86RF212 supports slotted acknowledgement operation. this mode is invoked by setting register bit slotted_operation (register 0x2c, xah_ctrl_0) to 1. if an acknowledgment (ack) frame is to be transmitted in rx_aack mode, the radio transceiver expects a rising edge on pin 11 (slp _tr) to actually start the transmission. during this waiting period the transcei ver reports success_wait_for_ack through register bits trac_status (r egister 0x02, xah_ctrl_0), see figure 5-9. the minimum d elay between the occurrence of interrupt irq_3 (trx_end) and pin start of the ack frame in slotted operation is 3 symbol periods. figure 5-10 illustrates the timing of an rx _aack transactio n in slotted operation. the acknowledgement frame is ready to transmit 3 symbol times after the reception of the last symbol of a data or mac command frame, indicated by irq_3. the transmission of the acknowledgement frame is initiated by t he microcontroller with the rising edge of pin 11 (slp_tr) and starts t tr10 later.
53 8168b-mcu wireless-02/09 AT86RF212 figure 5-10. example timing of an rx_aack transaction for slotted operation busy_rx_aack frame on air rx_aack_on busy_rx_aack trx_state frame type rx_aack_on rx/tx rx tx trx_end irq rx t irq data frame (ack=1) ack frame (frame pending = 0) sfd slp_tr slp_tr accepted t tr10 3 symbols ... success_wait_for_ack success trac_status time 5.2.3.6 timing a general timing example of an rx_aack transaction is shown in figure 5-11. in this example a d ata frame with an ack request is received. the AT86RF212 changes to state busy_rx_aack after sfd detection. t he completion of the frame reception is indicated by a trx_end interrupt. the interrupts irq_2 (tx_start) and irq_5 (ami) are disabled in this example. the ack frame is automatically transmitted after aturnaroundtime (12 symbols), assuming default ac knowledgment frame start timing. the interrupt latency t 9 is specified in section 10.4. figure 5-11. example timi ng of an rx_aack transaction frame on air rx_aack_on busy_rx_aack trx_state frame type rx_aack_on rx/tx rx tx trx_end irq rx t irq data frame (ack=1) ack frame (frame pending = 0) sfd ... success_wait_for_ack success trac_status aturnaroundtime (aack_ack_time) time 5.2.4 tx_aret_on ? transmit with automatic retry and csma-ca retry the tx_aret extended operating mode suppor ts the frame transmission process as defined by ieee 802.15.4?2006. it is invoked as described in 5.2.1 by writing tx_aret_ on to register subfield trx_cmd (register 0x02, trx_state). if a transmission is initiated in tx_aret mode, the AT86RF212 executes the csma-ca algorithm, as defined by ieee 802. 15.4?2006, sect ion 7.5.1.4. if the cca reports idle, the frame is transmitted from the frame buffer.
54 8168b-mcu wireless-02/09 AT86RF212 if an acknowledgement frame is requested, t he radio transceiver checks for an ack reply automatically. the csma-ca based tran smission process is repeated as long as no valid acknowledgement is received or the number of frame retransmissions (max_frame_retries) is exceeded. the completion of the tx_aret transaction is indicated by the irq_3 (trx_end) interrupt, see section 5.2.5. description the implemented tx_aret algorithm is shown in figure 5-12. prior to i nvoking tx_aret mode, see section 5.2.1, the basic configuration steps as descri bed in 5.2.2 shall be executed. it is further recommended to write the psdu transmit data to the frame buffer in advance. the transmit start event may either come from a rising edge on pin 11 (slp_tr) or by writing a tx_start command to register subfield trx_cmd (register 0x02, trx_state). if the csma-ca algorithm detects a busy c hannel, this process is repeated up to max_csma_retries (register 0x2c, xah_ctrl_0). in case that csma-ca does not detect a clear channel after max_csma_retries, it aborts the tx_aret transaction, issues interrupt irq_3 (trx_end), and returns channel_access_failure in register bi ts trac_status (register 0x02, trx_state). during transmission of a frame, the radio tran sceiver parses bit 5 (ack request) of the mac header (mhr) frame to check w hether an ack reply is expected. if no ack is expected, the radio transceiver issues irq_3 (trx_end) directly after the frame transmission has been completed. the register bits trac_status (register 0x02, trx_state) are set to success. if an ack is expected, after transmission the r adio transceiver automatically switches to receive mode waiting for a valid ack reply (i.e. matching sequence number and correct fcs). after receiving a valid ack frame the frame pending subfield of this frame is parsed and the status register bits trac_status are updated to success or success_data_pending accordingly, refer to table 5-15. at the same time, the entire tx_a ret transaction is terminated and interrupt irq_3 (trx_end) is issued. if no valid ack is received within the timeout period, refer to section 5.2.4.1, the radio transceive r retries the entire transaction, (csma-ca based frame transmission) until the maximum number of frame retransmissions is exceeded, see register bits max_frame_retries (register 0x2c, xah_ctrl_0). in that case, the trac_status is set to no_ack, the tx _aret transaction is terminated, and interrupt irq_3 (trx_end) is issued. table 5-15 summarizes the extended operating mode result codes in register subfield trac_status (r egister 0x02, trx_stat e) with respect to the tx_aret transaction.
55 8168b-mcu wireless-02/09 AT86RF212 figure 5-12. flow diagram of tx_aret failure success y n issue irq_3 (trx_end) y n n trx_state = tx_aret_on trx_state = busy_tx_aret trac_status = invalid max_csma_retries == 7 ? csma-ca, csma_ctr++ cca result csma_ctr > max_csma_retries ? n ack requested ? ack receive until timeout ack valid? frame transmit, frm_ctr++ trac_status = no_ack trac_status = success data pending ? n y y trac_status = channel_access_failure frm_ctr > max_frame_retries ? csma_ctr = 0 trac_status = success_data_pending y y n trx_state = tx_aret_on frm_ctr = 7 frm_ctr = 0 frame start tx_start or slp_tr=h
56 8168b-mcu wireless-02/09 AT86RF212 table 5-15. tx_aret interpretation of trac_status register bits value name description 0 success the transaction was responded by a valid ack, or, if no ack is requested, after a successful frame transmission. 1 success_data_pending equivalent to success and indicating that the frame pending bit (see section 6.1.2.2) of the receiv ed acknowledgment frame was set. 3 channel_access_failure channel is still busy after max_csma_retries of csma-ca. 5 no_ack no acknowledgement frame was received during all retry attempts. 7 invalid entering tx_aret mode until irq_3 (trx_end). a value of max_csma_retries = 7 initia tes an immediate tx_aret transaction without performing csma-ca. this supports beacon-enabled network operation. furthermore by ignoring the value of m ax_frame_retries only a single attempt is made to transmit the frame. note that the acknowledgment receive proc edure does not overwrite the frame buffer content. transmit data in the frame buffer is not modified during the entire tx_aret transaction. received frames other than the expected ack frame are discarded automatically. 5.2.4.1 acknowledgment timeout if an acknowledgment (ack) frame is expected after frame transmission, the AT86RF212 sets a timeout until which a valid ack frame must have been arrived. this timeout macackwaitduration is defined according to [1] as follows: macackwaitduration [symbol periods] = aunitbackoffperiod + aturnaroundtime + physhrduration + 6 physymbolsperoctet, where 6 represents the number of phy header octets plus the number of psdu octets in an acknowledgment frame. specifically for the implem ented phy modes (see section 7.1), this formula results in the followin g values: ? bpsk: macackwaitduration = 120 symbol periods ? o-qpsk: macackwaitduration = 54 symbol periods note that for any phy mode the unit [symbol period] refers to the symbol duration of the appropriate synchronization header, see section 7.1.3 for further information regarding symbol pe riod. 5.2.4.2 timing a timing example of a tx_aret transaction is shown in figure 5-13. in the example sho wn, a data frame with an acknowledgment request is to be transmitted. the frame
57 8168b-mcu wireless-02/09 AT86RF212 transmission is started by pin 11 (slp_tr). as min_be is set to zero, the initial csma- ca backoff period has length zero too. thus the csma-ca duration time t csma-ca only consists of 8 symbols of cca measurement period. if cca returns idle (assumed here), the frame is transmitted. after that, the AT86RF212 switches to receive mode and expects an acknowledgement response, which is indicated by register subfield trac_status (register 0x02, trx_state) set to success_wait _for_ack. after a period of aturnaroundtime + aunitbackoff the transmission of the ack frame must have started. during the entire transaction including frame transmit, wa it for ack and ack receive, the radio transceiver status register trx_status (register 0x01, trx_status) signals busy_tx_aret. a successful reception of the acknowledgmen t frame is indicated by interrupt irq_3 (trx_end). the status register trx_stat us (register 0x01, trx_status) changes back to tx_aret_on. at the same time , register trac_status changes to success or to success_data_pending, if the frame pending subfield of the acknowledgment frame was set to 1. figure 5-13. example timing of a tx_aret transaction (without pending data bit set in ack frame) frame on air tx_aret_on busy_tx_aret trx_state frametype tx_aret_on rx/tx rx trx_end irq typ. delays 16 s slp_tr tx t irq data frame (ack=1) ack frame register settings: 0x2c: max_frame_retries=0 0x2c: max_csma_retries=0 0x2e: min_be=0 32 s t csma-ca (8 symbols) tx csma-ca rx time succ. / invalid success trac_status invalid aturnaroundtime (12 symbols) ack start timeout 20 symbols 5.2.5 interrupt handling the interrupt handling in the extended operating mode is similar to the basic operating mode. interrupts can be enabled by setting the appropriate bit in register 0x0e (irq_mask). for rx_aack and tx_aret the following interrupt s inform about the status of a frame reception and transmission: ? irq_2 (rx_start) ? irq_3 (trx_end) ? irq_5 (ami) for rx_aack mode, it is recommended to enable only interrupt irq_3 (trx_end). this interrupt is issued only if the frame filter (see section 6.2) reports a matching address an d the fcs is valid (see section 6.3). the usage of other interrupts is optional.
58 8168b-mcu wireless-02/09 AT86RF212 on reception of a frame, the rx_start inte rrupt indicates the detection of a correct synchronization header (shr) and a non-zero phy header (phr). this interrupt is issued after the phr. ami indicates address match, refer to filter rules in section 6.2. the t rx_end interrupt is always generated after completing a tx_aret transaction. after that, the return code can be read from subfield trac_status (register 0x02, trx_state). several interrupts are automatically suppressed by the radio transceiver during tx_aret transaction. in contrast to section 6.6, the cca algorithm (part of csma-ca) doe s not generate interrupt irq_4 (cca_e d_done). furthermore, the interrupts rx_start and ami are not generated during the tx_aret acknowledgment receive process. 5.2.6 register description r egister summary the following registers control the extended operating mode: table 5-16. register summary reg.-addr. register name description 0x01 trx_status radio transceiver status, cca result 0x02 trx_state radio transceiver state control, tx_aret status 0x04 trx_ctrl_1 tx_auto_crc_on 0x08 phy_cc_cca cca mode control, see section 6.6.6 0x09 cca_thres cca ed threshold settings, see section 6.6.6 0x17 xah_ctrl_1 rx_aack control 0x20 ? 0x2b frame filter configuration - short address, pan id and ieee address - see section 6.2.3 0x2c xah_ctrl_0 tx_aret control, retries value control 0x2d csma_seed_0 csma-ca seed value 0x2e csma_seed_1 csma-ca seed value, rx_aack control 0x2f csma_be csma-ca backoff exponent control register 0x01 (trx_status) : the read-only register trx_status provides the current state of the radio transceiver. a state change is initiated by writing a st ate transition command to register bits trx_cmd (register 0x02, trx_state). table 5-17. register 0x01 (trx_status) bit 7 6 5 4 name cca_done cca_status reserved trx_status[4] read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name trx_status[3] trx_status[2] trx_status[1] trx_status[0] read/write r r r r reset value 0 0 0 0
59 8168b-mcu wireless-02/09 AT86RF212 ? bit 7 ? cca_done refer to section 6.6, not updated in extended operating mode ? bit 6 ? cca_status refer to section 6.6, not updated in extended operating mode ? bit 5 ? reserved ? bit 4:0 ? trx_status the register bits trx_status signals the current radio transceiver status. table 5-18. radio transceiver status register bits value state description 0x00 p_on 0x01 busy_rx 0x02 busy_tx 0x06 rx_on 0x08 trx_off (clk mode) 0x09 pll_on (tx_on) 0x0f (1) sleep 0x11 busy_rx_aack 0x12 busy_tx_aret 0x16 rx_aack_on 0x19 tx_aret_on 0x1c rx_on_noclk 0x1d rx_aack_on_noclk 0x1e busy_rx_aack_noclk 0x1f (2) state_transition_in_progress trx_status all other values are reserved notes: 1. in sleep state r egisters are not accessible. 2. do not try to initiate a further stat e change while the radio transceiver is in state_transition_in_progress state. register 0x02 (trx_state) : the AT86RF212 radio transceiver states are controlled via register trx_state using register bits trx_cmd. a successful stat e transition shall be confirmed by reading register bits trx_status (register 0x01, trx_status). the read-only register bits trac_status indicate the status or result of an extended operating mode transaction. table 5-19. register 0x02 (trx_state) bit 7 6 5 4 name trac_status[2] trac_status[1] trac_status[0] trx_cmd[4] read/write r r r r/w reset value 0 0 0 0
60 8168b-mcu wireless-02/09 AT86RF212 bit 3 2 1 0 name trx_cmd[3] trx_cmd[2] trx_cmd[1] trx_cmd[0] read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:5 ? trac_status the status of the rx_aack and tx_aret proc edure is indicated by register bits trac_status. details of the algorithm and a description of the status information are given in sections 5.2.3 and 5.2.4. table 5-20. trac_status transaction status register bits value description rx_aack tx_aret 0 (1) success x x 1 success_data_pending x 2 success_wait_for_ack x 3 channel_access_failure x 5 no_ack x 7 (1) invalid x x trac_status all other values are reserved note: 1. even though the reset value for register bits trac_status is 0, the rx_aack and tx_aret procedures set the register bits to trac_status = 7 (invalid) when it is started. ? bit 4:0 ? trx_cmd a write access to register bits trx_cmd in itiates a radio transceiver state transition: table 5-21. state control register register bits value state description 0x00 nop 0x02 tx_start 0x03 force_trx_off 0x04 (1) force_pll_on 0x06 rx_on 0x08 trx_off (clk mode) 0x09 pll_on (tx_on) 0x16 rx_aack_on 0x19 tx_aret_on trx_cmd all other values are reserved and mapped to nop note: 1. force_pll_on is not valid for st ates sleep, p_on, reset, trx_off, and all *_noclk states, as well as state_transition_in_progress towards these states. register 0x04 (trx_ctrl_1) : the trx_ctrl_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver.
61 8168b-mcu wireless-02/09 AT86RF212 table 5-22. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode spi_cmd_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en refer to section 9.4. ? bit 6 ? irq_2_ext_en refer to section 9.5. ? bit 5 ? tx_auto_crc_on if set, register bit tx_auto_crc_on enables the automatic fcs generation. for further details refer to section 6.3. ? bit 4 ? rx_bl_ctrl refer to section 9.6. ? bit 3:2 ? spi_cmd_mode refer to section 4.4.1. ? bit 1 ? irq_mask_mode refer to section 4.7. ? bit 0 ? irq_polarity refer to section 4.7. register 0x17 (xah_ctrl_1) : the xah_ctrl_1 register is a control register for extended operating mode. table 5-23. register 0x17 (xah_ctrl_1) bit 7 6 5 4 name reserved csma_lbt_mode aack_fltr_res_ft aack_upld_res_ft read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name reserved aack_ack_time aack_prom_mode reserved read/write r r/w r/w r reset value 0 0 0 0 ? bit 7 ? reserved ? bit 6 ? csma_lbt_mode refer to section 6.7.3.
62 8168b-mcu wireless-02/09 AT86RF212 ? bit 5 ? aack_fltr_res_ft this register bit shall only be set if aack_upld_res_ft = 1. if aack_fltr_res_ft = 1, reserved frame types are filtered like data frames as specified in ieee 802.15.4-2006. reserved frame types are explained in ieee 802.15.4 section 7.2.1.1.1. interrupt irq_5 (ami) is issued upon passing the frame filter, see section 6.2. if aack_fltr_ res_ft = 0, the received reserved frame is only checked for a valid fcs. ? bit 4 ? aack_upld_res_ft if aack_upld_res_ft = 1, received frames marked as reserved frames are further processed. for these frames, interrupt irq_ 3 (trx_end) is generated, if the fcs is valid. in conjunction with the configuration bit aack_fltr_res_ft set, these frames are handled like ieee 802.15.4 compliant data frames during rx_aack transaction. otherwise, if aack_upld_res_ft = 0, frames with a reserved frame type are blocked. ? bit 3 ? reserved ? bit 2 ? aack_ack_time according to ieee 802.15.4, section 7.5.6.4.2 the transmission of an ac knowledgment frame shall commence 12 symbol periods ( aturnaroundtime ) after the reception of the last symbol of a data or mac command frame. this is achieved with the reset value of the register bit aack_ack_time. alternatively, if aack_ack_time = 1, t he acknowledgment response time is reduced according to table 5-24. table 5-24. short ack response time (aack_ack_time = 1) phy mode ack response time [symbol periods] bpsk-20, oqpsk-{100,200,400} 2 bpsk-40, oqpsk-{250,500,1000} 3 the reduced ack response time is particularly useful for the high data rate modes, refer to section 7.1.4. ? bit 1 ? aack_prom_mode register bit aack_prom_mode enables the promiscuous mode, within the rx_aack mode; refer to ieee 802. 15.4-2006 section 7.5.6.5. if this bit is set, incoming frames with a va lid phr generate interrupt irq_3 (trx_end) even if the third level filter rules do not match or the fcs is not valid. however, register bit rx_crc_valid (register 0x06) is set accordingly. if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by regist er bit aack_dis_ack (register 0x2e, csma_seed_1). ? bit 0 ? reserved register 0x2c (xah_ctrl_0) : register 0x2c (xah_ctrl_0) is a control register for extended operating mode.
63 8168b-mcu wireless-02/09 AT86RF212 table 5-25. register 0x2c (xah_ctrl_0) bit 7 6 5 4 name max_frame_retries[3:0] read/write r/w reset value 0 0 1 1 bit 3 2 1 0 name max_csma_retries[2:0] slotted_operation read/write r/w r/w reset value 1 0 0 0 ? bit 7:4 ? max_frame_retries the setting of max_frame_retries specifies the number of attempts in tx_aret mode to automatically retransmit a frame, when it was not acknowledged by the recipient. ? bit 3:1 ? max_csma_retries max_csma_retries specifies the number of retries in tx_aret mode to repeat the csma-ca procedure before the transaction gets cancelled. according to ieee 802.15.4, the valid range of max_csma_retries is [0, 1, ?, 5]. a value of max_csma_retries = 7 initiates an immediate frame transmission without performing csma-ca. this may especially be required for slotted acknowledgement operation. max_csma_retries = 6 is reserved. ? bit 0 ? slotted_operation if set, register bit slotted_operat ion enables rx_aack acknowledgment generation in slotted operation mode, refer to section 5.2.3.5. usi ng rx_aack mode in networks operating in beacon or slotted mode, refer to ieee 802.15.4-2006, section 5.5. 1, register bit slotted_ operation indicates that acknowledgement frames are to be sent on backoff slot boundaries (slotted acknowledgement). if this register bit is set, the acknowledgement frame transmission is initiated by the microcontroller, using the rising edge of pin 11 (slp_tr). register 0x2d (csma_seed_0) : the csma_seed_0 register is a control regi ster for tx_aret and contains a part of the csma seed for the csma-ca algorithm. table 5-26. register 0x2d (csma_seed_0) bit 7 6 5 4 3 2 1 0 name csma_seed[7:0] read/write r/w reset value 1 1 1 0 1 0 1 0 ? bit 7:0 ? csma_seed this register contains the lower 8 bit of the csma_seed, bits [7:0]. the higher 3 bit are part of register bits csma_seed_1 (regis ter 0x2e, csma_seed_1). csma_seed is
64 8168b-mcu wireless-02/09 AT86RF212 the seed for the random number generati on that determines the length of the backoff period in the csma-ca algorithm. it is recommended to initialize registers csma_seed with random values. this can be done using register bits rnd_value (register 0x06, phy_rssi), refer to section 9.2. register 0x2e (csma_seed_1) : the csma_seed_1 register contains a part of the csma seed for the csma-ca algorithm, as well as control bits for the frame filter and rx_aack transaction. table 5-27. register 0x2e (csma_seed_1) bit 7 6 5 4 name aack_fvn_mode aack_fvn_mode aack_set_pd aack_dis_ack read/write r/w r/w r/w r/w reset value 0 1 0 0 bit 3 2 1 0 name aack_i_am_coord csma_seed[10] csma_seed[9] csma_seed[8] read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 7:6 ? aack_fvn_mode the frame control field of the mac header (mhr) contains a frame version subfield. the setting of aack_fvn_mode specifies the frame filtering and acknowledgement behavior of the AT86RF212. according to the content of these register bits the radio transceiver passes frames with a specif ic frame version number, number group, or independent of the frame version number. thus the register bit aack_fvn_mode defines the maximum acceptable frame version. received frames with a higher frame version number than configured do not pass the frame filter and thus are not acknowledged. table 5-28. frame version subfield dependent frame acknowledgment register bits value description 0 acknowledge frames with version number 0 1 acknowledge frames with version number 0 or 1 2 acknowledge frames with version number 0 or 1 or 2 aack_fvn_mode 3 acknowledge independent of frame version number note that the frame version field of the acknowledgment frame is set to 0x00 according to ieee 802.15.4-2006, section 7.2.2.3.1 acknowledgment frame mhr fields. ? bit 5 ? aack_set_pd the content of aack_set_pd bit is copied into the frame pending subfield of the acknowledgment frame if the ack is the answer to a data request mac command frame. in addition, if register bits aack_fvn_ mode (register 0x2e, csma_seed_1) are configured to accept frames with a frame version other than 0 or 1, the content of register bit aack_set_pd is also copied into the frame pending subfield of the acknowledgment frame for any mac command fram e with a frame version of 2 or 3 that
65 8168b-mcu wireless-02/09 AT86RF212 have the security enabled subfield set to 1. this is done in the assumption that a future version of the standard [1] might change the length or structure of the auxiliary security header, so it would not possible to safely detect whether the mac command frame is actually a data request command or not. ? bit 4 ? aack_dis_ack if this bit is set, no acknowledgment fr ames are transmitted in rx_aack extended operating mode, even if requested. ? bit 3 ? aack_i_am_coord this register bit has to be set if the node is a pan coordinator. it is used for frame filtering in rx_aack. if i_am_coord = 1 and if only source addressing fields are included in a data or mac command frame, the frame shall be accepted only if the device is the pan coordinator and the source pan identifier matches macpanid, for details refer to ieee 802.15.4, section 7.5.6.2 (third-level filter rule 6). ? bit 2:0 ? csma_seed these register bits are the higher 3-bit of the csma_seed, bits [10:8]. the lower part is in register 0x2d (csma_seed_0), see register csma_seed_0 for details. register 0x2f (csma_be) : table 5-29. register 0x2f (csma_be) bit 7 6 5 4 name max_be[3] max_be[2] max_be[1] max_be[0] read/write r/w r/w r/w r/w reset value 0 1 0 1 bit 3 2 1 0 name min_be[3] min_be[2] min_be[1] min_be[0] read/write r/w r/w r/w r/w reset value 0 0 1 1 ? bit 7:4 ? max_be register bits max_be defines the maximu m value of the backoff exponent in the csma-ca algorithm. it equals macmaxbe , refer to [1], section 7.5.1.4, table 71. valid values are [4?d8, 4?d7, ? , 4?d3]. ? bit 3:0 ? min_be register bits min_be defines the minimum value of the backoff exponent in the csma- ca algorithm. it equals to macminbe, refer to [1], section 7.5.1.4, table 71. valid values are [max_be, (max_be ? 1), ? , 4?d0]. note ? if min_be = 0 and max_be = 0, the cca backoff period is always set to 0.
66 8168b-mcu wireless-02/09 AT86RF212 6 functional description 6.1 introduction ? ieee 802.15.4-2006 frame format figure 6-1 provides an overview of the phy sical layer (phy) frame structure as defined by the ieee 802.15.4-2006 standard. figure 6-2 shows the medium access control lay er (mac) frame structure. figure 6-1. ieee 802.15.4 frame format ? phy layer frame structure max. 127 octets phy payload phy service data unit (psdu) 1 octet (phr) 5 octets synchronization header (shr) phy protocol data unit (ppdu) preamble sequence sfd frame length phy payload mac protocol data unit (mpdu) 6.1.1 phy protocol data unit (ppdu) 6.1.1.1 synchroni zation header (shr) the shr consists of a four-octet preamble field (all zero), followed by a single octet start-of-frame delimiter (sfd). during tran smit, the shr is automatically generated by the AT86RF212, thus the frame buffer shall contain phr and psdu only, see section 4.3.2. the transmission of the shr requires 40 symbols for a transmission with bpsk modulation and 10 symbols for a transmission with o-qpsk modulation, respectively. table 6-1 illustrates the shr duration depending on the selected data rate, see also se ction 10.5. as the spi data rate is usually higher than the over-the-air data rate, this allows the microcontroller to initiate a transmissi on before the frame buffer write access is completed. during frame reception, the shr is used fo r synchronization purposes. the matching sfd determines the beginning of the phr and the following psdu payload data. 6.1.1.2 phy header (phr) the phy header is a single octet following the shr. the least significant 7 bits denote the frame length of the following psdu, while the most significant bit of that octet is reserved, and shall be set to 0 for ieee 802.15.4 compliant frames. even though the msb is reserved, AT86RF212 is able to transmit and receive this bit. in transmit mode, the phr needs to be suppl ied as the first octet during frame buffer write access, see section 4.3.2. in re ceive mode, the phr is returned as the first octet during frame buffer read access, see section 4.3.2. 6.1.1.3 phy payload (phy service data unit, psdu) the psdu has a variable length between one and 127 octets. the psdu contains the mac protocol data unit (mpdu), where the last two octets are used for the frame check sequence (fcs), see section 6.3.
67 8168b-mcu wireless-02/09 AT86RF212 6.1.1.4 timing summary table 6-1 shows timing information for the above mentioned frame structure depending on the selected data rate. table 6-1. ppdu timing duration phy mode psdu bit rate [kbit/s] header bit rate [kbit/s] shr [s] phr [s] max. psdu [ms] 20 20 2000 400 50.8 bpsk (1) 40 40 1000 200 25.4 100 100 300 80 10.16 o-qpsk (1) 250 250 160 32 4.064 200 100 300 80 5.08 400 100 300 80 2.54 500 250 160 32 2.032 o-qpsk (2) 1000 250 160 32 1.016 notes: 1. compliant to ieee 802.15.4-2006, see [1] 2. high data rate modes, see chapter 7.1.4 6.1.2 mac protocol data unit (mpdu) figure 6-2 shows the frame structure of the mac layer. figure 6-2. ieee 802.15.4-2006 frame format ? mac layer frame structure frame control field 2 octets frame pending reserved frame version ack request pan id compr. destination addressing mode source addressing mode security enabled (mfr) mac service data unit (msdu) mac protocol data unit (mpdu) mac payload fcs frame type 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mac header (mhr) fcf addressing fields sequence number 2 octets crc-16 0/5/6/10/14 octets auxiliary security header 0/4/6/8/10/12/14/16/18/20 octets destination pan id destination address source pan id source address 6.1.2.1 mac header (mhr) the mac header consists of the frame cont rol field (fcf), a sequence number, and the addressing fields of variable length. 6.1.2.2 frame control field (fcf) the fcf occupies the first two octets of the mpdu. bit [2:0] : describe the ?frame type?. table 6-2 summarizes frame types defined by [1], se ction 7.2.1.1.1.
68 8168b-mcu wireless-02/09 AT86RF212 table 6-2. frame type field frame type value b 2 b 1 b 0 value description 000 0 beacon 001 1 data 010 2 acknowledge 011 3 mac command 100 ? 111 4 ? 7 reserved these bits are used for frame filtering by the third level filter rules, refer to section 7.2.1.1.1 of [1]. bit 3 indicates whether security processing applie s to this frame. this field is evaluated by the frame filter. bit 4 is the ?frame pending? subfield. this field can be set in an acknowledgment frame to indicate to the node receiving the acknowledgment frame that the node sent the acknowledgment frame has more data to send. bit 5 forms the ?acknowledgment request? subfield. if this bit is set within a data or mac command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time s pecified by ieee 802.15.4 (i.e. within 12 symbols for nonbeacon-enabled networks). bit 6 : the ?pan id compression? subfield i ndicates that in a frame where both the destination and source addresses are present, the pan id is omitted from the source addressing field. this bit is evaluated by the frame filter of the AT86RF212. bit [9:7] : reserved bit [11:10] : the ?destination addressing mode? subfield describes the format of the destination address of the frame. the valu es of the address modes are summarized in table 6-3, according to ieee 802.15.4: table 6-3. destination and source addressing mode addressing mode value b 11 b 10 value description 00 0 pan identifier and address fields are not present. 01 1 reserved 10 2 address field contains a 16-bit short address. 11 3 address field contains a 64-bit extended address. if the destination address mode is either 2 or 3, i.e. if the destination address is present, the addressing field consists of a 16-bit pan id first, followed by either the 16-bit or 64- bit address as defined by the mode. bit [13:12] : the ?frame version? subfield specifies the version number corresponding to the frame, see table 6-4. these bits are re served in ieee- 802.15.4-2003. this subfield shall be set to 0x00 to indicate a frame compatible with ieee 802.15.4-2003 and 0x01 to indicate an ieee 802.15.4 frame. all other subfield values shall be reserved for future use. see [1], section 7.2.3 for details on frame compatibility.
69 8168b-mcu wireless-02/09 AT86RF212 table 6-4. frame version field frame version value b 13 b 12 value description 00 0 frames are compatible with ieee 802.15.4-2003 01 1 frames are compatible with ieee 802.15.4-2006 10 2 reserved 11 3 reserved bit [15:14] is the ?source addressing mode? subfield, with similar meaning as ?destination addressing mode?. the addressing field description bits of the fcf (bits 0?2, 3, 6, 10?15) affect the AT86RF212 frame filter, see section 6.2. 6.1.2.3 frame compatibility betwe en ieee 802.15.4 rev. 2003 and 2006 all unsecured frames according to ieee 802.15.4-2006 are compatible with unsecured frames compliant with ieee 802.15.4-2003, with two exceptions: a coordinator realignment command frame with the channel page field present (see [1], section 7.3.8) and any frame with a mac payload field larger than amaxmacsafepayloadsize octets . compatibility for secured frames is shown in table 6-5, which identifies the security operating modes for ieee 802.15.4-2003 and ieee 802.15.4-2006. table 6-5. frame compatibility frame control field bit assignments security enabled b 3 frame version b 13 b 12 description 0 00 no security. frames are compatible between ieee 802.15.4-2003 and ieee 802.15.4-2006. 0 01 no security. frames are not compatible between ieee 802.15.4-2003 and ieee 802.15.4-2006. 1 00 secured frame formatted according to ieee 802.15.4-2003. this type of frame is not supported in ieee 802.15.4-2006. 1 01 secured frame formatted according to ieee 802.15.4-2006 6.1.2.4 sequence number the one-octet sequence number following the fcf identifies a particular frame, so that duplicated frame transmissions can be detecte d. while operating in rx_aack states, the received frame content of this field is copied into the acknowledgment frame. 6.1.2.5 addressing fields the addressing field carries several addresses used for address matching indication. the destination address (if present) is always first, followed by the source address (if present). each address field consists of the pan id and a device address. if both addresses are present, and the ?pan id compression? subfield in the fcf is set to one, the source pan id is omitted.
70 8168b-mcu wireless-02/09 AT86RF212 note that in addition to these general rule s, ieee 802.15.4 further restricts the valid address combinations for the different mac frame types. for example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for ac knowledgment frames. the frame filter in the AT86RF212 has been designed to apply to ieee 802.15.4 compliant frames. it can be configured to handle other frame formats and exceptions. 6.1.2.6 auxiliary security header the auxiliary security header terminates the mhr. this field has a variable length and specifies information required for security processing, including how the frame is actually protected (security level) and whic h keying material from the mac security pib is used (see [1], section 7.6.1). this field s hall be present only if the security enabled subfield b3, see 6.1.2.3, is set to one. for details on formatting, see 7.6.2 of [1]. 6.1.2.7 mac service data unit (msdu) this is the actual mac payload. it is usually structured according to the individual frame type descriptions in ieee 802.15.4 standard. 6.1.2.8 mac footer (mfr) the mac footer consists of a two-octet fr ame checksum (fcs), for details refer to section 6.3. 6.2 frame filter frame filtering is a procedure that evaluates whether or not a received frame matches predefined criteria, like source or desti nation address or frame types. a filtering procedure as described in ieee 802.15.4-2006 chapter 7.5.6.2 (thi rd level of filtering) is applied to the frame to accept a received frame and to generate the address match interrupt irq_5 (ami). the AT86RF212 frame filter passes only frames that satisfy all of the following requirements/rules (q uote from ieee 802.15.4-2006, 7.5.6.2): 1. the frame type subfield shall not contain a reserved frame type. 2. the frame version subfield s hall not contain a reserved value. 3. if a destination pan identifier is included in the frame, it shall match macpanid or shall be the broadcast pan identifier (0xffff). 4. if a short destination address is included in the frame, it shall match either macshortaddress or the broadcast addres s (0xffff). otherwise, if an extended destination address is included in the frame, it shall match aextendedaddress. 5. if the frame type indicates that the frame is a beacon frame, the source pan identifier shall match macpanid unless macpanid is equal to 0x ffff, in which ca se the beacon frame shall be accepted regardless of the source pan identifier. 6. if only source addressing fields are in cluded in a data or mac command frame, the frame shall be accepted only if the device is the pan coordinator and the source pan identifier matches macpanid. moreover the AT86RF212 has two additional requirements: 7. the frame type shall indicate that the fr ame is not an acknowledgment (ack) frame. 8. at least one address field must be configured.
71 8168b-mcu wireless-02/09 AT86RF212 address matching, indicated by interrupt irq_ 5 (ami), is furthermore controlled by the fcf of a received frame according to the following rule: if destination addressing mode is 0/1 and s ource addressing mode is 0, see section 6.1.2.2, no interrupt irq_5 is generated. this causes that no acknowledgement frame is ann ounced. for backward compatibility with ieee 802.15.4-2003, the third level filter rule 2 (frame version) can be disabled by register bits aack_fvn_mode (register 0x2e, csma_seed_1). frame filtering is available in extended and basic operating modes. a frame that passes the frame filter generates the in terrupt irq_5 (ami), if not masked. notes ? filter rule 1 is affected by register bits aack_fltr_res_ft and aack_upld_res_ft, see section 6.2.3. ? filter rule 2 is affected by register bits aack_fvn_mode, see section 6.2.3. 6.2.1 configuration the frame filter is configured by setting the appropriate address variables and several additional properties as described in table 6-6. table 6-6. frame filter configuration register address register bits name description 0x20,0x21 0x22,0x23 0x24 ? 0x2b 7:0 short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 set macshortaddress , macpanid aextendedaddress as described in [1] 0x17 1 aack_prom_mode 0 : disable promiscuous mode 1 : enable promiscuous mode 0x17 4 aack_upld_res_ft 0 : disable reserved frame type reception 1 : enable reserved frame type reception 0x17 5 aack_fltr_res_ft filter reserved frame types like data frame type, see section 6.2.2 0 : disable 1 : enable 0x2e 7:6 aack_fvn_mode frame acceptance criteria depending on fcf frame version number b00 : accept only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames b01 : accept only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2006 b10 : accept only frames with version number 0 or 1 or 2 b11 : accept all frames, independent of the fcf frame version number
72 8168b-mcu wireless-02/09 AT86RF212 6.2.2 handling of reserved frame types reserved frame types as described in 5.2.3.3 are treated according to bits aack_upl d_res_ft and aack_fltr_res_ft of register 0x17 (xah_ctrl_1) with 3 options: 1. aack_upld_res_ft = 1, aack_fltr_res_ft = 0: frames of reserved frame type with correc t fcs are indicated by the interrupt irq_3 (trx_end). no further frame filtering is applied on these frames. interrupt irq_5 (ami) is never generated and no acknowledgment is sent. 2. aack_upld_res_ft = 1, aack_fltr_res_ft = 1: if aack_fltr_res_ft = 1, any frame with a reserved frame type is treated by the rx_aack frame filter as an ieee 802.15.4 compliant data frame. this implies the generation of the interrupt irq_5 (ami) upon address matches. 3. aack_upld_res_ft = 0 any frame with a reserved frame type is blocked. 6.2.3 register description r egister 0x17 (xah_ctrl_1) : the xah_ctrl_1 register is a control register for extended operating mode. table 6-7. register 0x17 (xah_ctrl_1) bit 7 6 5 4 name reserved csma_lbt_mode aack_fltr_res_ft aack_upld_res_ft read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name reserved aack_ack_time aack_prom_mode reserved read/write r r/w r/w r reset value 0 0 0 0 ? bit 7 ? reserved ? bit 6 ? csma_lbt_mode refer to section 6.7.3. ? bit 5 ? aack_fltr_res_ft this register bit shall only be set if aack_upld_res_ft = 1. if aack_fltr_res_ft = 1, any frame with a reserved frame type is treated by the rx_aack frame filter as an ieee 802.15.4 compliant data frame. if aack_fltr_res_ft = 0, the received reserved frame is only checked for a valid fcs. see 6.2.2 for details. ? bit 4 ? aack_upld_res_ft if aack_upld_res_ft = 1, received frames which are identified as reserved frames will not be blocked. see 6.2.2 for details. ? bit 3 ? reserved
73 8168b-mcu wireless-02/09 AT86RF212 ? bit 2 ? aack_ack_time refer to section 5.2.3.3. ? bit 1 ? aack_prom_mode refer to section 5.2.6. ? bit 0 ? reserved register 0x20 (short_addr_0) : this register contains the lower 8 bit of t he 16-bit short address fo r frame filter address recognition, bits [7:0]. table 6-8. register 0x20 (short_addr_0) bit 7 6 5 4 3 2 1 0 name short_address_0[7:0] read/write r/w reset value 1 1 1 1 1 1 1 1 register 0x21 (short_addr_1) : this register contains the higher 8 bit of the 16-bit short address for frame filter address recognition, bits [15:8]. table 6-9. register 0x21 (short_addr_1) bit 7 6 5 4 3 2 1 0 name short_address_1[7:0] read/write r/w reset value 1 1 1 1 1 1 1 1 register 0x22 (pan_id_0) : this register contains the lower 8 bit of the mac pan id for frame filter address recognition, bits [7:0]. table 6-10. register 0x22 (pan_id_0) bit 7 6 5 4 3 2 1 0 name pan_id_0[7:0] read/write r/w reset value 1 1 1 1 1 1 1 1 register 0x23 (pan_id_1) : this register contains the higher 8 bit of the mac pan id for frame filter address recognition, bits [15:8]. table 6-11. register 0x23 (pan_id_1) bit 7 6 5 4 3 2 1 0 name pan_id_1[7:0] read/write r/w reset value 1 1 1 1 1 1 1 1
74 8168b-mcu wireless-02/09 AT86RF212 register 0x24 (ieee_addr_0) : this register contains bits [7:0] of the 64-bit ieee extended addr ess for frame filter address recognition. table 6-12. register 0x24 (ieee_addr_0) bit 7 6 5 4 3 2 1 0 name ieee_addr_0[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x25 (ieee_addr_1) : this register contains bits [15:8] of the 64-bit ieee extended address for frame filter address recognition. table 6-13. register 0x25 (ieee_addr_1) bit 7 6 5 4 3 2 1 0 name ieee_addr_1[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x26 (ieee_addr_2) : this register contains bits [23:16] of th e 64-bit ieee extended address for frame filter address recognition. table 6-14. register 0x26 (ieee_addr_2) bit 7 6 5 4 3 2 1 0 name ieee_addr_2[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x27 (ieee_addr_3) : this register contains bits [31:24] of th e 64-bit ieee extended address for frame filter address recognition. table 6-15. register 0x27 (ieee_addr_3) bit 7 6 5 4 3 2 1 0 name ieee_addr_3[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x28 (ieee_addr_4) : this register contains bits [39:32] of th e 64-bit ieee extended address for frame filter address recognition.
75 8168b-mcu wireless-02/09 AT86RF212 table 6-16. register 0x28 (ieee_addr_4) bit 7 6 5 4 3 2 1 0 name ieee_addr_4[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x29 (ieee_addr_5) : this register contains bits [47:40] of th e 64-bit ieee extended address for frame filter address recognition. table 6-17. register 0x29 (ieee_addr_5) bit 7 6 5 4 3 2 1 0 name ieee_addr_5[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x2a (ieee_addr_6) : this register contains bits [55:48] of th e 64-bit ieee extended address for frame filter address recognition. table 6-18. register 0x2a (ieee_addr_6) bit 7 6 5 4 3 2 1 0 name ieee_addr_6[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x2b (ieee_addr_7) : this register contains bits [63:56] of th e 64-bit ieee extended address for frame filter address recognition. table 6-19. register 0x2b (ieee_addr_7) bit 7 6 5 4 3 2 1 0 name ieee_addr_7[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x2e (csma_seed_1) : the csma_seed_1 register is a control register for rx_aack and cont ains a part of the csma seed for the csma-ca algorithm, as well as control bits for the frame filter and rx_aack transaction. table 6-20. register 0x2e (csma_seed_1) bit 7 6 5 4 name aack_fvn_mode aack_fvn_mode aack_set_pd aack_dis_ack read/write r/w r/w r/w r/w reset value 0 1 0 0
76 8168b-mcu wireless-02/09 AT86RF212 bit 3 2 1 0 name aack_i_am_coord csma_seed_1 csma_seed_1 csma_seed_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 7:6 ? aack_fvn_mode the frame control field of the mac header (mhr) contains a frame version subfield. the setting of aack_fvn_mode specifies the frame filtering and acknowledgement behavior of the AT86RF212. according to the content of these register bits the radio transceiver passes frames with a specific set of frame version numbers. thus the register bit aack_fvn_mode defines the maximum acceptable frame version. received frames with a higher frame version number than configured do not pass the frame filter and thus are not acknowledged. table 6-21. frame version subfield dependent frame acceptance register bits value description 0 accept frames with version number 0 1 accept frames with version number 0 or 1 2 accept frames with version number 0 or 1 or 2 aack_fvn_mode 3 accept frames independent of frame version number ? bit 5 ? aack_set_pd refer to section 5.2.6. ? bit 4 ? aack_ dis_ack refer to section 5.2.6. ? bit 3 ? aack_i_am_coord refer to section 5.2.6. ? bit 2:0 ? csma_seed_1 refer to section 5.2.6. 6.3 frame check sequence (fcs) a fcs mechanism employing a 16-bit international telecommunication union - telecommunication standardization sector (itu-t) cyclic redundancy check (crc) can be used to detect errors in frames. 6.3.1 overview the fcs is intended for use at the mac layer in order to detect corrupted frames. it is computed by applying an itu-t crc polynomial to all transmitted/received bytes following the length field (mhr and msdu fields). the fcs has a length of 16 bit and is located in the last two octets of the psdu. by default, the AT86RF212 generates and inserts the fcs octets autonomously during transmit process. this behavior can be disabled by setting register bit tx_auto_crc_on = 0 (register 0x04, trx_ctrl_1). an automatic fcs check is always performed during frame reception.
77 8168b-mcu wireless-02/09 AT86RF212 6.3.2 crc calculation the crc polynomial used in i eee 802.15.4 networks is defined by 1 )( 51216 16 +++= xxxxg . the fcs shall be calculated for transmission using the following algorithm: let 1 2 2 1 1 0 )( ? ? ? ? ++++= k k k k bxbxbxbxm k be the polynomial representing the sequence of bits for which the checksum is to be computed. multiply m(x) by 16 x , giving the polynomial 16 )()( xxmxn ?= . divide )( xn modulo 2 by the generator polynomial, )( 16 xg , to obtain the remainder polynomial, 15 14 14 1 15 0 ... )( rxrxrxrxr ++++= the fcs field is given by the coefficients of the remainder polynomial, )( xr . example: considering a 5-octet ack frame, the mhr field consists of 0100 0000 0000 0000 0101 0110 . the leftmost bit (b 0 ) is transmitted first in time. the fcs would be 0010 0111 1001 1110 . the leftmost bit (r 0 ) is transmitted first in time. 6.3.3 automatic fcs generation the automatic fcs generation is enabled with register bit tx_auto_crc_on = 1. this allows the AT86RF212 to compute the fcs autonomously. for a frame with a frame length field specified as n (3 ? n ? 127), the fcs is calculated on the first n-2 octets in the frame buffer, and the resulting fcs octets are transmitted in place of the last two octets of the frame buffer. 6.3.4 automatic fcs check basic and extended operating modes are provided with an automatic fcs check for received frames. register bit rx_crc_valid (register 0x06, phy_rssi) is set to one, if the fcs of a received frame is valid. in addition, bit 7 of byte rx_status is set accordingly, refer to section 4.3.2. in extended operating mo de, the rx_aack procedure does not accept a frame, if the corresponding fcs is not valid, and no trx_end interrupt is issued. when operating in tx_aret mode, the fcs of a received ack is automatically checked. if it is not correct, the ack is not accepted, refer to section 5.2.4 for automated retries. 6.3.5 register description regis ter 0x04 (trx_ctrl_1) : the trx_ctrl_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver, see table 6-22.
78 8168b-mcu wireless-02/09 AT86RF212 table 6-22. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode irq_mask_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en refer to section 9.4.3. ? bit 6 ? irq_2_ext_en refer to section 9.5.2. ? bit 5 ? tx_auto_crc_on the automatic fcs generation is performed with register bit tx_auto_crc_on = 1, which is the reset value. ? bit 4 ? rx_bl_ctrl refer to section 9.6.2. ? bit 3:2 ? spi_cmd_mode refer to section 4.4.1. ? bit 1 ? irq_mask_mode refer to section 4.7.2. ? bit 0 ? irq_polarity refer to section 4.7.2. register 0x06 (phy_rssi) : the phy_rssi register is a multi-purpose regi ster to indicate fcs validity, to provide random numbers, and a rssi value. table 6-23. register 0x06 (phy_rssi) bit 7 6 5 4 name rx_crc_valid rnd_value rnd_value rssi[4] read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name rssi[3] rssi[2] rssi[1] rssi[0] read/write r r r r reset value 0 0 0 0
79 8168b-mcu wireless-02/09 AT86RF212 ? bit 7 ? rx_crc_valid reading this register bit indicates whether the last received frame has a valid fcs or not. the register bit is updated at the same time the irq_3 (trx_end) is issued and remains valid until the next shr detection. a value of ?1? corresponds to a valid fcs, a value of ?0? corresponds to an invalid fcs. ? bit 6:5 ? rnd_value refer to register description in section 9.1.8. ? bit 4:0 ? rssi refer to register description in section 6.4.4. 6.4 received signal strength indicator (rssi) the received signal strength indicator is characterized by: ? a dynamic range of 85 db ? a minimum rssi value of 0 ? a maximum rssi value of 28 6.4.1 overview the rssi is a 5-bit value indicating the received signal power in the selected channel, in steps of 3 db. no attempt is made to distinguish ieee 802.15.4 signals from others, only the received signal strength is evaluated. the rssi provides the basis for an ed measurement, see 6.5. 6.4.2 reading rssi in basic operating modes, the rssi value is valid in any receive state, and is updated at time intervals according to table 6-24. the current rssi value can be accessed by readi ng register bits rssi of register 0x06 (phy_rssi). table 6-24. rssi update interval phy mode update interval [s] bpsk-20 32 bpsk-40 24 o-qpsk 8 it is not recommended reading the rssi value when using the extended operating modes. instead, the automatically generated ed value should be used, see section 6.5. 6.4.3 data interpretation the rssi value is a 5-bit value, indicating t he receiver input power, in steps of 3 db and with a range of 0 - 28. a rssi value of 0 indicates a receiver input power less than rssi_base_val [dbm]. the value rssi_base_val itself depends on the phy mode, refer to section 7.1. for typical co nditions, it is shown in table 6-25. due to environmental conditions (temperatur e, voltage, semiconductor parameters, etc.), rssi_base_val has a maximum toleranc e of 5 db. this should be considered as a constant offset over the measurement range.
80 8168b-mcu wireless-02/09 AT86RF212 table 6-25. rssi_base_val phy mode rssi_base_val [dbm] maximum tolerance [db] bpsk with 300 kchip/s -100 5 bpsk with 600 kchip/s -99 5 o-qpsk with 400 kchip/s -98 5 o-qpsk with 1000 kchip/s, sine shaping (sin) -97 5 o-qpsk with 1000 kchip/s, raised cosine shaping (rc-0.8) -97 5 for a rssi value in the range of 1 to 28, the receiver input power can be calculated as follows: p rf = rssi_base_val [dbm] + 3.2 ? (rssi - 1) [dbm] figure 6-3. mapping between rssi value and receiver input power -105 -95 -85 -75 -65 -55 -45 -35 -25 -15 -5 0 2 4 6 8 1012141618202224262830 rssi received input power p rf [dbm] bpsk with 300 kchip/s bpsk with 600 kchip/s o-qpsk with 400 kchip/s o-qpsk with 1000 kchip/s (sin) o-qpsk with 1000 kchip/s (rc-0.8) 6.4.4 register description r egister 0x06 (phy_rssi) table 6-26. register 0x06 (phy_rssi) bit 7 6 5 4 name rx_crc_valid rnd_value rnd_value rssi[4] read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name rssi[3] rssi[2] rssi[1] rssi[0] read/write r r r r reset value 0 0 0 0
81 8168b-mcu wireless-02/09 AT86RF212 ? bit 7 ? rx_crc_valid refer to register description in section 6.3.5. ? bit 6:5 ? rnd_value refer to register description in section 9.1.8. ? bit 4:0 ? rssi the result of the automated rssi measurement is stored in register bits rssi. the value is updated at time intervals according to table 6-24 at any receive state. the valu e is a number between 0 and 28, indicating the received signal strength as a linear curve on a logarithmic input power scale (dbm) with a resolution of 3 db. a rssi value of 0 indicates a receiver input power less than rssi_base_val [dbm] (see table 6-25), a value of 28 an input powe r equal or larger than (rssi_base_val + 85) [dbm]. 6.5 energy detection (ed) the energy detection (ed) module is characterized by: ? 85 unique energy levels defined ? 1 db resolution 6.5.1 overview the receiver ed measurement (ed scan procedure) can be used as a part of a channel selection algorithm. it is an estimation of the received signal power within the bandwidth of an ieee 802.15.4 channel. no attempt is ma de to identify or decode signals on the channel. the ed value is calculated by aver aging rssi values over 8 symbol periods, with the exception of the high data rate modes, refer to 7.1.4. 6.5.2 measurement description there are two ways to initiate an ed measurement: ? manually, by writing an arbitrary value to register 0x07 (p hy_ed_level), or ? automatically, after detection of a valid shr of an incoming frame. for manually initiated ed measurements, the radio transceiver needs to be either in the state rx_on or busy_rx. the end of the ed measurement time (8 symbol periods) is indicated by the interrupt irq_4 (cca_ed_done) and the measurement result is stored in register 0x07 (phy_ed_level). in order to avoid interference with an automatically initiated ed measurement, the shr detection can be disabled by setting register bit rx_pdt_dis (register 0x15, rx_syn), refer to section 7.2. note that it i s not recommended to manually initiate an ed measurement when using the extended operating mode. an automated ed measurement is started upon shr detection. the end of the automated measurement is not signaled by an interrupt. when using the basic operating mode, a valid ed value (register 0x07, phy_ed_level) of the currently received fram e is accessible not later than 8 symbol periods after irq_2 (rx_start) plus a processing time of 12 s. the ed value remains valid until a new rx_start interrupt is generated by the next incoming frame or until another ed measurement is initiated.
82 8168b-mcu wireless-02/09 AT86RF212 when using the extended operating mode, it is useful to mask irq_2 (rx_start), thus the interrupt cannot be used as timing reference. a successful frame reception is signalized by interrupt irq_3 (trx_end). in this case, the ed value needs to be read within the time span of a next shr detection plus the ed measurement time in order to avoid overwrite of the current ed value. the values of the register 0x07 (phy_ed_level) are: table 6-27. register bit phy_ed_level interpretation phy_ed_level description 0xff reset value 0x00 ? 0x54 ed measurement result of the last ed measurement 6.5.3 data interpretation the phy_ed_level (ed) is an 8-bit register . the ed value of the AT86RF212 has a valid range from 0x00 to 0x54 (0 to 84) with a resolution of 1 db. values 0x55 to 0xfe do not occur and a value of 0xff indicates the reset value. a value of phy_ed_level = 0 indicates that the measured receiver input power is less than or equal to rssi_base_val [dbm] (refer to table 6-25). for a n ed value in the range of 0 to 84, the receiver input power can be calculated as follows: p rf = rssi_base_val [dbm] + 1.05 ? ed [dbm] figure 6-4. mapping between receiver input power and ed value -105 -95 -85 -75 -65 -55 -45 -35 -25 -15 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 phy_ed_level (register 0x07) received input power p rf [dbm] bpsk with 300 kchip/s bpsk with 600 kchip/s o-qpsk with 400 kchip/s o-qpsk with 1000 kchip/s (sin) o-qpsk with 1000 kchip/s (rc-0.8) 6.5.4 interrupt handling interrupt irq_4 (cca_ed_done) is issued at the end of a manually initiated ed measurement.
83 8168b-mcu wireless-02/09 AT86RF212 note that an ed measurement should only be initiated in rx states but not in rx_aack states. otherwise, the radi o transceiver generates an irq_4 (cca_ed_done) without actually performing an ed measurement. 6.5.5 register description register 0x07 (phy_e d_level) the phy_ed_level register contains the result of an ed measurement. table 6-28. register 0x07 (phy_ed_level) bit 7 6 5 4 3 2 1 0 name ed_level[7:0] read/write r (1) reset value 1 1 1 1 1 1 1 1 note: 1. a write access is required for initiation of a manual ed measurement. bit 7:0 ? ed_level the minimum ed value (ed_level = 0) indica tes a receiver input power less than or equal to rssi_base_val [dbm]. the range is 85 db with a resolution of 1 db and an absolute accuracy of 5 db. a manual ed measurement can be initiated by a write access to the register. a value 0xff indicates that a measurement has never been started yet (reset value). the measurement duration is 8 symbol periods, see section 7.1.3. for high data rate modes, the automated measurement duration is reduced to 2 symbol periods, refer to 7.1.4. for manually initiated ed measurements in these mode s, the measurement time is still 8 symbol periods as long as the receiver is in rx_on state. a value out of {0x00, ?, 0x54} indicates the result of the last ed measurement. 6.6 clear channel assessment (cca) the main features of the clear channel assessment (cca) module are: ? all four cca modes are provided as defined in ieee 802.15.4-2006 ? adjustable threshold for energy detection algorithm 6.6.1 overview a cca measurement is used to detect a clear channel. four cca modes are specified by ieee 802.15.4-2006: table 6-29. cca mode overview cca mode description 1 energy above threshold . cca shall report a busy medium upon detecting any energy above the ed threshold. 2 carrier sense only . cca shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an ieee 802.15.4 compliant signal. the signal strength may be above or below the ed threshold.
84 8168b-mcu wireless-02/09 AT86RF212 cca mode description 0, 3 carrier sense with energy above threshold . cca shall report a busy medium using a logical combination of - detection of a signal with the modula tion and spreading characteristics of this standard and/or - energy above the ed threshold. where the logical operator may be c onfigured as either or (mode 0) or and (mode 3). 6.6.2 configuration and request the cca modes are configurable via register 0x08 (phy_cc_cca). when being in basic operating mode, a cca request can be initiated manually by setting cca_request = 1 (register 0x08, phy_cc_cca), if the AT86RF212 is in any rx state. the current channel status ( cca_status) and the cca completion status (cca_done) are accessible throu gh register 0x01 (trx_status). the end of a manually initiated cca (8 symbol periods plus 12 s processing delay), is indicated by the interrupt irq_4 (cca_ed_done). the sub-register cca_ed_thres of regist er 0x09 (cca_thres) defines the receive power threshold of the ? energy above threshold ? algorithm. the threshold is calculated by v_thres = (rssi_base_val + 2 ? cca_ed_thres) [dbm]. any received power above this level is interpreted as a busy channel. note that it is not recommended to manually initiate a cca request when using the extended operating mode. 6.6.3 data interpretation the current channel status (cca_status) and the cca completion status (cca_done) are accessible through register 0x01 (trx_status). note that register bits cca_done and cca_status are cleared in response to a cca_request. the completion of a measurement cycle is indicated by cca_done = 1. if the radio transceiver detected no signal (idle channel) during the cca evaluation period, the cca_status bit is set to 1, otherwise, it is set to 0. when using the ?energy above threshold? algorithm, a received power above v_thres level is interpreted as a busy channel. when using the ?carrier sense? algorithm (i.e. cca_mode = 0, 2, and 3), the AT86RF212 reports a busy channel upon det ection of a (phy mode specific) ieee 802.15.4 signal above the rssi_base_val (see table 6-25). the AT86RF212 is also capable of detecting signals below this value, but the detection probability decreases with decreasing signal power. it is almost zero at the radio transceivers sensitivity level (see chapter 0). 6.6.4 interrupt handling interrupt irq_4 (cca_ed_done) is issued at the end of a manually initiated cca measurement.
85 8168b-mcu wireless-02/09 AT86RF212 note ? a cca request should only be initiated in basic operating mode rx states. otherwise, the radio transceiver genera tes irq_4 (cca_ed_done) and sets the register bit cca_done = 1, without actually performing a cca measurement. 6.6.5 measurement time the response time of a manually initiated cca measurement depends on the receiver state. in rx_on state, the cca measurement is done over eight symbol periods and the result is accessible upon the event ir q_4 (cca_ed_done) or upon cca_done=1 (register 0x01, trx_status). in busy_rx state, the cca measurement duration depends on the cca mode and the cca request relative to the detection of the shr. the end of the cca measurement is indicated by irq_4 (cca_ed_done). the variation of a cca measurement period in busy_rx state is described in table 6-30. table 6-30. cca measurement period and access in busy_rx state cca mode request within ed measurement (1) request after ed measurement energy above threshold . 1 cca result is available after finishing automated ed measurement period. cca result is immediately available after request. carrier sense only . 2 cca result is immediately available after request. carrier sense with energy above threshold (and) . 3 cca result is available after finishing automated ed measurement period. cca result is immediately available after request. carrier sense with energy above threshold (or) . 0 cca result is available after finishing automated ed measurement period. cca result is immediately available after request. note: 1. after detecting the shr, an automated ed measurement is star ted with a length of 8 symbol periods (2 symbol periods for high rate phy modes), refer to 7.1.3. this automate d ed measurement must be fini shed to provide a result for the cca measurement. only one automated ed measurement per frame is performed. it is recommended to perform cca measur ements in rx_on state only. to avoid switching accidentally to busy_rx state, the shr detection can be disabled by setting register bit rx_pdt_dis (register 0x15, rx_syn), refer to section 7.2. the receiver remai ns in rx_on state to perform a cca measurement until the register bit rx_pdt_dis is set back to continue the frame reception. in this case, the cca measurement duration is 8 symbol periods. 6.6.6 register description regis ter 0x01 (trx_status) : two register bits of register 0x01 (trx_s tatus) indicate the status of the cca measurement.
86 8168b-mcu wireless-02/09 AT86RF212 table 6-31. register 0x01 (trx_status) bit 7 6 5 4 name cca_done cca_status reserved trx_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name trx_status trx_status trx_status trx_status read/write r r r r reset value 0 0 0 0 ? bit 7 ? cca_done this register indicates completion a cca measurement, which is additionally indicated by the interrupt irq_4 (cca_ed_done). note that register bit cca_done is cleared in response to a cca_request. table 6-32. cca algorithm status register bit value description 0 cca calculation not finished cca_done 1 cca calculation finished ? bit 6 ? cca_status after a cca request is completed, the result of the cca measurement is available in register bit cca_status. note that register bit cca_status is cleared in response to a cca_request. table 6-33. cca status result register bit value description 0 channel indicated as busy cca_status 1 channel indicated as idle ? bit 5 ? reserved ? bit 4:0 ? trx_status refer to section 5.1.5 and 5.2.6. register 0x08 (phy_cc_cca) : this register is provided to init iate and control a cca measurement. table 6-34. register 0x08 (phy_cc_cca) bit 7 6 5 4 name cca_request cca_mode[1] cca_mode[0] channel read/write w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name channel channel channel channel read/write r/w r/w r/w r/w reset value 0 1 0 1
87 8168b-mcu wireless-02/09 AT86RF212 ? bit 7 ? cca_request a manual cca measurement is initiated by setting cca_request = 1. the register bit is automatically cleared after requesting a cca measurement with cca_request = 1. ? bit 6:5 ? cca_mode the cca mode can be selected using register bits cca_mode. table 6-35. cca mode register bits value description 0 carrier sense or energy above threshold 1 energy above threshold 2 carrier sense only cca_mode 3 carrier sense and energy above threshold note that ieee 802.15.4?2006 cca mode 3 defines the logical combination of cca mode 1 and 2 with the logical operators and or or. this can be selected with: o cca_mode = 0 for logical operation or, and o cca_mode = 3 for logical operation and. ? bit 4:0 ? channel refer to section 7.8. register 0x09 (cca_thres) : this register sets the ed threshold level for cca. table 6-36. register 0x09 (cca_thres) bit 7 6 5 4 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 1 1 1 bit 3 2 1 0 name cca_ed_thres cca_ed_thres cca_ed_thres cca_ed_thres read/write r/w r/w r/w r/w reset value 0 1 1 1 ? bit 7:5 ? reserved ? bit 4:0 ? cca_ed_thres the cca mode 1 request indicates a busy channel if the measured received power is above (rssi_base_val + 2 ? cca_ed_thre s) [dbm]. cca modes 0 and 3 are logically related to this result.
88 8168b-mcu wireless-02/09 AT86RF212 6.7 listen before talk (lbt) 6.7.1 overview equipment using the AT86RF212 shall conform to the established regulations. with respect to the regulations in europe, csma-ca based transmission according to ieee 802.15.4 is not appropriate. in principle, trans mission is subject to low duty cycles (0.1 to 1 %). however, according to [4], equipment employing listen before talk (lbt) and adaptive frequency agility (afa) does not have to comply with duty cycle conditions. hence, lbt can be attractive in order to reduce network latency. minimum listening time a device with lbt needs to comply with a minimum listening time, refer to chapter 9.1.1.2 of [4]. prior transmission, the device must listen for a receive signal at or above the lbt threshold level to determine whether the intended channel is available for use, unless transmission is pursuing acknowledgement. a device using lbt needs to listen for a fixed period of 5 ms. if after this period the channel is free, transmission may immediat ely commence (i.e. no csma is required). otherwise, a new listening period of a randomly selected time span between 5 and 10 ms is required. the time resolution shall be approximately 0.5 ms. the last step needs to be repeated until a free channel is available. lbt threshold according to [4], the maxi mum lbt threshold for an ieee 802.15.4 signal is presumably -82 dbm, assuming a channel spacing of 1 mhz. 6.7.2 lbt mode the AT86RF212 supports the previously described lbt specific listening mode when operating in the extended operating mode. in particular, during tx_aret (see section 5.2.4), the csma-ca algorithm can be repla ced by the lbt listening mode, when setting register bit csma_lbt_mode (register 0x17, xah_ctrl_1). in this case, however, the register bits max_csma_retries (register 0x2c, xah_ctrl_0) as well as min_be and max_be (register 0x2f, csma_be) are ignor ed, implying that the listening mode will sustain, unless a clear channel has been fo und or the tx_aret transaction will be canceled. the latter can be achieved by setting trx_cmd to either force_pll_on or force_trx_off (register 0x02, trx_ state). all other aspects of tx_aret remain unchanged; refer to section 5.2.4. the lbt thre shold can be configured in the same way as for cca, i.e. via register bits cca_mode (register 0x08, phy_cc_cca) and register bits cca_ed_thres (register 0x09, cca_thres), refer to section 6.6. 6.7.3 register description regis ter 0x08 (phy_cc_cca) : this register is relevant for the measur ement mode when using lbt, i.e. selecting energy above threshold or carrier sense (cs) or combination of both.
89 8168b-mcu wireless-02/09 AT86RF212 table 6-37. register 0x08 (phy_cc_cca) bit 7 6 5 4 name cca_request cca_mode[1] cca_mode[0] channel read/write w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name channel channel channel channel read/write r/w r/w r/w r/w reset value 0 1 0 1 ? bit 7 ? cca_request not applicable for lbt, see section 6.6.6. ? bit 6:5 ? cca_mode the cca mode can be used in order to select the appropriate lbt measurement mode by using register bits cca_mode, refer to section 6.6. ? bit 4:0 ? channel refer to section 7.8. register 0x09 (cca_thres) : this register is relevant for the ed threshold when using lbt. table 6-38. register 0x09 (cca_thres) bit 7 6 5 4 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 1 1 1 bit 3 2 1 0 name cca_ed_thres cca_ed_thres cca_ed_thres cca_ed_thres read/write r/w r/w r/w r/w reset value 0 1 1 1 ? bit 7:5 ? reserved ? bit 4:0 ? cca_ed_thres for cca_mode = 1, a busy channel is indicated if the measured received power is above (rssi_base_val + 2 ? cca_ed_thres) [dbm]. cca_mode = 0 and 3 are logically related to this result. register 0x17 (xah_ctrl_1) : this register is relevant for enabling or disabling the lbt mode.
90 8168b-mcu wireless-02/09 AT86RF212 table 6-39. register 0x17 (xah_ctrl_1) bit 7 6 5 4 name reserved csma_lbt_mode aack_fltr_res_ft aack_upld_res_ft read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name reserved aack_ack_time aack_prom_mode reserved read/write r r/w r/w r reset value 0 0 0 0 ? bit 7 ? reserved ? bit 6 ? csma_lbt_mode if set to 0 (default), csma-ca algorithm is used during tx_aret for clear channel assessment. otherwise, the lbt specific listening mode is applied. ? bit 5 ? aack_fltr_res_ft refer to section 5.2.6. ? bit 4 ? aack_upld_res_ft refer to section 5.2.6. ? bit 3 ? reserved ? bit 2 ? aack_ack_time refer to section 5.2.6. ? bit 1 ? aack_prom_mode refer to section 5.2.6. ? bit 0 ? reserved 6.8 link quality indication (lqi) 6.8.1 requirements the ieee 802.15.4 standard defines the lqi as a characterization of the strength and/or quality of a received frame. the use of the lqi result by the network or application layer is not specified in this standard. the lqi value shall be an integer ranging from 0 to 255, with at least 8 unique values. the minimum and maximum lqi values (0 and 255) should be associated with the lowest and highest quality compliant signals, respectively, and lqi values in between should be uniformly distributed between these two limits. 6.8.2 implementation during symbol detection within frame reception, the AT86RF212 uses correlation results of multiple symbols in order to compute an estimate of the lqi value. this is motivated by the fact, that the mean value of the correlation result is inversely related to the probability of a detection error. lqi computation is automatically performed fo r each received frame, once the shr has been detected. lqi values are integers ranging from 0 to 255 as required by the ieee 802.15.4 standard.
91 8168b-mcu wireless-02/09 AT86RF212 6.8.3 obtaining the lqi value the lqi value is available, once the corresponding frame has been completely received. this is indicated by the interrupt irq_3 (trx_end). the value can be obtained by means of a frame buffer read access, see section 4.3.2. 6.8.4 remarks the reason for a low lqi value can be twofold: a low signal strength and/or high signal distortions, e.g. by interference and/or multipath propagation. high lqi values, however, indicate a sufficient signal strength and low signal distortions. note that the lqi value is almost always 255 for scenarios with very low signal distortions and a signal strength much greater than the sensitivity level. in this case, the packet error rate tends towards zero and increase of the signal strength, i.e. by increasing the transmission power, cannot decrease the error rate any further. received signal strength indication (rssi) or energy detection (ed) can be used to evaluate the signal strength and the link margin. zigbee networks often require identification of the ?best? routing between two nodes. lqi and rssi/ed can be applied, depending on the optimization criteria. if a low frame error rate (corresponding to a high throughput) is the optimization criteria, then the lqi value should be taken into cons ideration. if, however, the tar get is a low transmission power, then the rssi/ed value is also helpful. various combinations of lqi and rssi/ed are possible for routing decisions. as a rule of thumb, information on rssi/ed is useful in order to differentiate between links with high lqi values. however, transmission links with low lqi values should be discarded for routing decisions even if the rssi/ed values are high, since it is merely an information about the received signal strengt h whereas the source can be an interferer.
92 8168b-mcu wireless-02/09 AT86RF212 7 module description 7.1 physical layer modes 7.1.1 spreading, modulation, and pulse shaping the AT86RF212 supports various physical layer (phy) modes independent of the rf channel selection. symbol mapping along with chip spreading, modulation, and pulse shaping is part of the digital base band processor, see figure 7-1. figure 7-1. base band transmitter architecture symbol mapping & chip spreading modulation bpsk/o-qpsk pulse shaping ppdu dac the combination of spreading, modulation, and pulse shaping are restricted to several combinations as shown in table 7-1. the at86rf 212 is fully compliant to the ieee 802.15.4 low data rate modes of 20 kbit/s or 40 kbit/s, employ ing binary phase-shift keying (bpsk) and spreading with a fixed chip rate of 300 kchip/s or 600 kchi p/s, respectively. the symbol rate is 20 ksymbol/s or 40 ksymbol/s, respectively. in both cases, pulse shaping is approximating a raised cosine filter with roll-off factor 1.0 (rc-1.0). for optional data rates according to ieee 802.15.4-2006, offset quadrature phase-shift keying (o-qpsk) is supported by the at86rf 212 with a fixed chip rate of either 400 kchip/s or 1000 kchip/s. at a chip rate of 400 kchip/s, pulse shaping is always a combination of both, half-sine shaping (sin) and raised cosine filtering with roll-off factor 0.2 (rc-0.2), according to ieee 802.15.4-2006 for the 868.3 mhz band. at a chip rate of 1000 kchip/s, pulse shaping is either half-sine filtering (sin) as specified in ieee 802.15.4-2006 [1], or, alternatively, raised cosine filtering with roll- off factor 0.8 (rc-0.8) as specified in ieee p802.15.4c [3]. for o-qpsk, the AT86RF212 supports spr eading according to ieee 802.15.4-2006 with data rates of either 100 kbit/s or 250 kbit/s depending on the chip rate, leading to a symbol rate of either 25 ksymbol/s or 62.5 ksymbol/s, respectively. additionally, the AT86RF212 supports two more spreading codes for o-qpsk with shortened code lengths. this leads to higher but non ieee 802.15.4-2006 compliant data rates during the psdu part of the frame with 200, 400, 500, and 1000 kbit/s. the proprietary high data rate modes are outlined in more detail in section 7.1.4. table 7-1. modulation and pulse shaping modulation chip rate [kchip/s] supported data rate for ppdu header [kbit/s] supported data rates for psdu [kbit/s] pulse shaping 300 20 20 rc-1.0 bpsk 600 40 40 rc-1.0 400 100 100, 200, 400 sin and rc-0.2 o-qpsk 1000 250 250, 500, 1000 sin or rc-0.8
93 8168b-mcu wireless-02/09 AT86RF212 7.1.2 configuration the phy mode can be selected by setting appropriate register bits of register 0x0c (trx_ctrl_2), refer to section 7.1.5. during configuration, the transceiver needs to be in state t rx_off. 7.1.3 symbol period within ieee 802.15.4 and, accordingly, within this document, time references are often specified in units of symbol periods, leading to a phy mode independent description. table 7-2 shows the duration of the symbol period. note that for the proprietary high data rat e modes, the symbol period is (by def inition) the same as the symbol period of the corresponding base mode. table 7-2. duration of the symbol period modulation psdu data rate [kbit/s] duration of symbol period [s] 20 50 bpsk 40 25 100, 200, 400 40 o-qpsk 250, 500, 1000 16 7.1.4 proprietary high data rate modes the main features are: ? high data rates up to 1000 kbit/s ? support of basic and extended operating mode ? reduced ack timing (optional) 7.1.4.1 overview the AT86RF212 supports alternative data rates of {200, 400, 500, 1000} kbit/s for applications not necessarily target ing ieee 802.15.4 compliant networks. the high data rate modes utilize the same rf channel bandwidth as the ieee 802.15.4-2006 sub-1 ghz o-qpsk modes. higher data rates are achieved by modified o-qpsk spreading codes having re duced code lengths. the lengths are reduced by the factor 2 or by the factor 4. for o-qpsk with 400 kchip/s, this leads to a data rate of 200 kbit/s (2-fold) and 400 kbit/s (4-fold), respectively. for o-qpsk with 1000 kchip/s, the resulting da ta rate is 500 kbit/s (2-fold) and 1000 kbit/s (4-fold), respectively. due to the decreased spreading factor, the sensitivity of the receiver is reduced. section 10.7, parameter 10.7.1, shows typical values of the sensitivity for different data rates. note that the sensitivity values of the high data rate modes are provided for a maximum psdu length of 127 octets. 7.1.4.2 high data rate frame structure in order to allow robust frame synchronization, high data rate modulation is restricted to the psdu part only. the ppdu header (the preamble, the sfd, and the phr field) are transmitted with the ieee 802.15.4 o-qpsk rate of either 100 kbit/s or 250 kbit/s (basic rates), see figure 7-2.
94 8168b-mcu wireless-02/09 AT86RF212 figure 7-2. high date rate frame structure preamble sfd phr psdu basic rate transmission: 100 kbit/s 250 kbit/s high rate transmission: {200, 400} kbit/s {500, 1000} kbit/s due to the overhead caused by the ppdu header and the fcs, the effective data rate is less than the selected data rate, depending on the length of the psdu. a graphical representation of the effective data rate is shown in figure 7-3. figure 7-3. effective data rate of the o-qpsk modes 0 20 40 60 80 100 120 0 100 200 300 400 500 600 700 800 900 b [kbit/s] psdu length in octets netto bit rate b 1000 kbit/s 500 kbit/s 250 kbit/s 400 kbit/s 200 kbit/s 100 kbit/s consequently, high data rate transmission is useful for large psdu lengths due to the higher effective data rate, or in order to reduce the power consumption of the system. 7.1.4.3 high date rate mode options reduced acknowledgment time if register bit aack_ack_time (register 0x17, xah_ctrl_1) is set, the acknowledgment time is reduced to the dur ation of 2 symbol periods for 200 and 400 kbit/s, and to 3 symbol periods for 500 and 1000 kbit/s, refer to table 5-24. otherwise, it defaults to 12 symbol period s according to ieee 802.15.4. receiver sensitivity control the different data rates between ppdu header (shr and phr) and phy payload (psdu) cause a different sensitivity between header and payload. this can be adjusted by defining sensitivity threshold levels of t he receiver. with a sensitivity threshold level set, the AT86RF212 does not synchronize to frames with an rssi level below that threshold. refer to section 7.2.3 for a configuration of the sensitivity threshold with regi ster 0x15 (rx_syn).
95 8168b-mcu wireless-02/09 AT86RF212 scrambler for data rates 1000 kbit/s and 400 kbit/s, additional chip scrambling is applied per default, in order to mitigate data dependent spectral properties. scrambling can be disabled if bit oqpsk_scram_en (regist er 0x0c, trx_ctrl_2) is set to 0. energy detection the ed measurement time span is 8 symbol periods according to ieee 802.15.4, see section 7.1.3. for frames operated at a higher data rate, the ed measurement period is reduced to 2 symbol periods taking reduced frame durations into account. this means, the ed measurement time is 80 s for modes 200 kbit/s and 400 kbit/s, and 32 s for modes 500 kbit/s and 1000 kbit/s. carrier sense for clear channel as sessment, ieee 802.15.4-2006 specif ies several modes which may either apply energy above threshold or carrier sense (cs) or a combination of both. since signals of the high data rate modes are not co mpliant to ieee 802.15.4-2006, cs is not supported, when the AT86RF212 is operating in these modes. however, ?energy above threshold? is supported. link quality indicator (lqi) for the high data rate modes, the link quality value does not contain useful information and should be discarded. 7.1.5 register description regis ter 0x0c (trx_ctrl_2) : the trx_ctrl_2 register controls the phy mode settings. note that during configuration, the transceiver needs to be in state trx_off. table 7-3. register 0x0c (trx_ctrl_2) bit 7 6 5 4 name rx_safe_mode trx_off_avdd_en oqpsk_scram_en oqpsk_sub1_rc_en read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name bpsk_oqpsk sub_mode oqpsk_data_rate oqpsk_data_rate read/write r/w r/w r/w r/w reset value 0 1 0 0 ? bit 7 ? rx_safe_mode refer to section 9.7.2. ? bit 6 ? trx_off_avdd_en refer to section 5.1.4.3.
96 8168b-mcu wireless-02/09 AT86RF212 ? bit 5 ? oqpsk_scram_en if set to 1 (reset value), the scrambler is enabled for oqpsk_data_rate = 2 and bpsk_oqpsk = 1 (o-qpsk is active). otherwise, the scrambler is disabled. note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly required to align different transceivers wi th oqpsk_scram_en in order to assure interoperability. ? bit 4 ? oqpsk_sub1_rc_en the bit is only relevant for sub_mode = 1 and bpsk_oqpsk = 1. if set to 0 (reset value), pulse shaping is half-sine filtering for o-qpsk. if set to 1, pulse shaping is rc-0.8 filtering for o-qpsk transmission with 1000 kchip/s. compared with half-sine filtering, side-lobes are reduced at the expense of an increased peak to average ratio (~ 1 db). this mode is particularly suitable for the chinese 780 mhz band. note that during reception, this bit is not evaluated within the AT86RF212, so it is not explicitly required to align different tran sceivers with oqpsk_sub1_rc_en in order to assure interoperability. it is very likely, t hat this also holds for any ieee 802.15.4-2006 compliant o-qpsk transceiver in the 915 mhz band, since the ieee 802.15.4-2006 requirements are fulfilled for both types of shaping. ? bit 3 ? bpsk_oqpsk if set to 0 (reset value), bpsk transmi ssion and reception is applied. if set to 1, o-qpsk transmission and reception is applied. note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly required to align different transceivers with bpsk_oqpsk in order to assure interoperability. ? bit 2 ? sub_mode if set to 1 (reset value), the chip ra te is 1000 kchip/s for bpsk_oqpsk = 1 and 600 kchip/s for bpsk_oqpsk = 0. it permits data ra tes out of {250, 500, 1000} kbit/s, or 40 kbit/s, respectively. this mode is particularly suitable for the 915 mhz band. for o- qpsk transmission, pulse shaping is either half-sine shaping or rc-0.8 shaping, depending on oqpsk_sub1_rc_en. if set to 0, the chip rate is 400 kchip/s for bpsk_oqpsk = 1 and 300 kchip/s for bpsk_oqpsk = 0. it permits data rates out of {100, 200, 400} kbi t/s, or 20 kbit/s, respectively. this mode is particularly suitable for the 868.3 mhz band. for o-qpsk transmission, pulse shaping is always the combination of half-sine shaping and rc-0.2 shaping. note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly required to align different transceivers with sub_mode in order to assure interoperability. ? bit 1:0 ? oqpsk_data_rate these register bits control the o-qpsk data ra te during the psdu part of the frame, as depicted by table 7-4. the reset value is oqpsk_data_rate = 0. note that du ring reception, these bits are evaluated within the AT86RF212, so it is explicitly required to align different tr ansceivers with oqpsk_data_rate in order to assure interoperability.
97 8168b-mcu wireless-02/09 AT86RF212 table 7-4. o-qpsk data rate during psdu o-qpsk data rate [kbit/s] register bits value sub_mode = 0 sub_mode = 1 0 100 250 1 200 500 oqpsk_data_rate 2, 3 400 1000 in table 7-5, all phy modes supported by the AT86RF212 are summarized with the relevant setting for each b it of register trx_ctrl_2. the character ?-? means, the bit entry is not relevant for the particular phy mode. table 7-5. register 0x0c (trx_ctrl_2) bit alignment register 0x0c, bit phy mode 76543210 compliance bpsk-20 - - - - 0 0 - - ieee 802.15.4: channel page 0, channel 0 bpsk-40 - - - - 0 1 - - ieee 802.15.4: channel page 0, channel 1 to 10 oqpsk-sin-rc-100 - - - - 1 0 0 0 ieee 802.15.4-2006: channel page 2, channel 0 oqpsk-sin-rc-200 - - - - 1 0 0 1 proprietary oqpsk-sin-rc-400-scr-on - - 1 - 1 0 1 - proprietary, scrambler on oqpsk-sin-rc-400-scr-off - - 0 - 1 0 1 - proprietary, scrambler off oqpsk-sin-250 - - - 0 1 1 0 0 ieee 802.15.4-2006: channel page 2, channel 1 to 10 oqpsk-sin-500 - - - 0 1 1 0 1 proprietary oqpsk-sin-1000-scr-on - - 10111- proprietary, scrambler on oqpsk-sin-1000-scr-off - - 00111- proprietary, scrambler off oqpsk-rc-250 - - - 1 1 1 0 0 ieee p802.15.4c (china): channel page 5, channel 0 to 3 oqpsk-rc-500 - - - 1 1 1 0 1 proprietary oqpsk-rc-1000-scr-on - - 11111- proprietary, scrambler on oqpsk-rc-1000-scr-off - - 01111- proprietary, scrambler off 7.2 receiver (rx) 7.2.1 overview the AT86RF212 transceiver is split into an analog radio front-end and a digital domain, see figure 1-1. referring to the receiver part of the analog section, the differential rf signal is amplified by a low noise amplifier (lna) and split into quadrature signals by a poly-phase filter (ppf). two mixer circuits convert the quadrature signal down to an intermediate frequency. channel selectivity is achieved by an integrated band-pass filter (bpf). the subsequent analog-to-digital converter (adc) samples the receive signal and additionally generates a digital rssi signal, see section 6.4. the adc output is then further processed by the digital baseband receiver (rx bbp) which is part of the digital domain.
98 8168b-mcu wireless-02/09 AT86RF212 the bbp performs further filter ing and signal processing. in rx_on state the receiver searches for the synchronization header. once the synchronization is established and the sfd is found the received signal is demodulated and provided to the frame buffer. the receiver performs a state change indicate d by register bits trx_status (register 0x01, trx_status) to busy_rx. once the whole frame is received, the receiver switches back to rx_on to listen on the channel. a similar scheme applies to the extended operating mode. the receiver is designed to handle frequency and symbol rate errors up to 60 ppm, refer to section 10.5, parameter 10.5.7. several status information are generated during the receive process: lqi, ed, and rx_status. they are automatically appended during frame read access, refer to section 4.3.2. some information is also available through register access, e.g. ed value (register 0x07, phy_ed_level) and f cs co rrectness (re gister 0x06, phy_rssi). the extended operating mode of the AT86RF212 supports frame filtering and pending data indication. the frame receive procedure including the radio transceiver setup for reception and reading psdu data from the frame buffer is described in section 8.1. 7.2.2 configuration in basic operating mode, the receiver is enabled by writing command rx_on to register bits trx_cmd (register 0x02, trx_state) in states trx_off or pll_on. in extended operating mode, the receiver is enabled for rx_aack operation from state pll_on by writing the command rx_aack_on. there is no additional configuration required to receive ieee 802.15.4 compliant frames when using the basic operating mode. however, the frame reception in the extended operating mode requires further register c onfigurations. for details refer to section 5.2.2. for specific applications the receiver can be configured to handle critical environments, to simplify the interaction with the microcontroller or to operate different data rates. the AT86RF212 receiver has an outstanding sensitivity performance. at certain conditions (interference floor, high data rate modes, refer to section 7.1.4), it may be useful to manually decrease this sensitiv ity. this is achieved by adjusting the synchronization header detector threshold us ing register bits rx_pdt_level (register 0x15, rx_syn). received signals with a rssi value below the threshold do not activate the demodulation process. furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. a dynamic frame buffer protection is enabled with register bit rx_safe_mode (register 0x0c, trx_ctrl_2) set, see section 9.7. the receiver rem ains in rx_on or rx_aack_on state until the whole frame is uploaded by the microcontroller, indicated by /sel = h during the spi frame receive mode. the frame buffer content is only pr otected if the fcs is valid. a static frame buffer protection is enabled with register bit rx_pdt_dis (register 0x15, rx_syn) set. the receiver remain s in rx_on or rx_aack_on state and no further shr is detected until the regi ster bit rx_pdt_dis is set back.
99 8168b-mcu wireless-02/09 AT86RF212 7.2.3 register description table 7-6. register 0x19 (rf_ctrl_1) bit 7 6 5 4 name rf_mc[3] rf_mc[2] rf_mc[1] rf_mc[0] read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:4 ? rf_mc these register bits provide the matching cont rol of the differential rf pins (rfn, rfp) by switching capacitances to ground, see figure 2-2. each step increases the cap acitance by 36 ff at each pin. the capacitance setting at the rf pins is valid for both rx and tx operation. table 7-7. rf pin matching control register bits value capacitance at rf pins [ff] 0 0 1 36 2 72 3 108 ? rf_mc 15 540 ? bit 3:0 ? reserved register 0x15 (rx_syn) : this register controls the sensit ivity threshold of the receiver. table 7-8. register 0x15 (rx_syn) bit 7 6 5 4 name rx_pdt_dis reserved reserved reserved read/write r/w r r r reset value 0 0 0 0 bit 3 2 1 0 name rx_pdt_level[3] rx_pdt_level[2] rx_pdt_level[1] rx_pdt_level[0] read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? rx_pdt_dis rx_pdt_dis = 1 prevents the reception of a frame even if the radio transceiver is in receive mode. an ongoing frame reception is not affected.
100 8168b-mcu wireless-02/09 AT86RF212 ? bit 6:4 ? reserved ? bit 3:0 ? rx_ pdt_level with these register bits, the receiver can be desensitized such that frames with an rssi level below the threshold level (if rx_pdt_l evel > 0) are not received. the threshold level can be calculated according to the following formula: rx_thres = rssi_base_val + 3 ? rx_pdt_level, for rx_pdt_level > 0 the rssi_base_value is described in section 6.4.3. if r egister bits rx_pdt_level = 0 (reset value), this feature is disabled which corresponds to the highest sensitivity. if register bits rx_pdt_level > 0, the current consumption of the receiver in states rx_on and rx_aack_on is reduced by 500 a. 7.3 transmitter (tx) 7.3.1 overview the AT86RF212 transmitter utilizes a direct up-conversion topology. the digital transmitter (tx bbp) generates the in-phase (i) an d quadrature (q) component of the modulation signal. a digital-to-analog converter (dac) forms the analog modulation signal. a quadrature mixer pair converts the analog modulation signal to the rf domain. the power amplifier (pa) provides signal power delivered to the differential antenna pins (rfp, rfn). both, the lna the pa are internally connected to the bidirectional differential antenna pins so that no external antenna switch is needed. using the default settings, the pa incorporates an equalizer to improve its linearity. the enhanced linearity keeps the spectral side lobes of the transmit spectrum low in order to meet the requirements of the european 868.3 mhz band. if the pa boost mode is turned on, the equalizer is disabled. this allows to deliver a higher transmit power of up to 10 dbm at the cost of higher spectral side lobes and higher harmonic power. in basic operating mode a transmission is st arted from pll_on state by either writing tx_start to register bits trx_cmd (regist er 0x02, trx_state) or by a rising edge of slp_tr. in extended operating modes, a transmission might be started automatically depending on the transaction phase of either rx _aack or tx_aret, refer to section 5.2. 7.3.2 frame transmit procedure the frame transmit procedure including writing psdu data into the frame buffer and initiating a transmission is described in section 8.2. 7.3.3 spectrum masks the AT86RF212 can be operated in different frequency bands, using different power levels, modulation schemes, chip rates, and pulse shaping filters. the occupied bandwidth of transmit signals depends on the chosen mode of operation, refer to table 7-9. kno wledge of modulation bandwidth, power spectrum, and side lobes is essential for proper system setup, i.e. non-overlapping channel spacing.
101 8168b-mcu wireless-02/09 AT86RF212 table 7-9. modulation, pulse shaping, and occupied bandwidth modulation chip rate [kchip/s] pulse shaping 99% occupied bandwidth [khz] 6 db bandwidth [khz] 20 db bandwidth [khz] 300 rc-1.0 385 310 430 bpsk 600 rc-1.0 750 535 825 400 sin and rc-0.2 370 290 400 sin 1210 840 1230 o-qpsk 1000 rc-0.8 1210 870 1300 figure 7-4 to figure 7-8 show power spectra for different parameter combinations listed in table 7-9. note that not all combinati ons are compliant with ieee 802.15.4-2006. the spectra were captured using default settings of AT86RF212. the resolution bandwidth of the spectrum analyzer was set to 30 khz. the video bandwidth was set to 10 khz. figure 7-4. spectrum of bpsk with chip rate of 300 kchip/s -70 -60 -50 -40 -30 -20 -10 0 912 913 914 915 916 frequency [mhz] power [dbm]
102 8168b-mcu wireless-02/09 AT86RF212 figure 7-5. spectrum of bpsk with chip rate of 600 kchip/s -70 -60 -50 -40 -30 -20 -10 0 912 913 914 915 916 frequency [mhz] power [dbm] figure 7-6. spectrum of o-qpsk with chip rate of 400 kchip/s -70 -60 -50 -40 -30 -20 -10 0 912 913 914 915 916 frequency [mhz] power [dbm]
103 8168b-mcu wireless-02/09 AT86RF212 figure 7-7. spectrum of o-qpsk with chip ra te of 1000 kchip/s and sinewave pulse shaping -70 -60 -50 -40 -30 -20 -10 0 910 912 914 916 918 frequency [mhz] power [dbm] figure 7-8. spectrum of o-qpsk with chip ra te of 1000 kchip/s and raised cosine pulse shaping -70 -60 -50 -40 -30 -20 -10 0 910 912 914 916 918 frequency [mhz] power [dbm]
104 8168b-mcu wireless-02/09 AT86RF212 figure 7-4 to figure 7-8 illustrate typical spectra of the transmitted signals of the at86r f212 and do not claim any limits. refer to the local authority bodies (fcc, etsi etc.) for further details about definition of power spectral density masks, definition of spurious emission, allowed modulation bandwidth, transmit power, and its limits. 7.3.4 tx output power the maximum output power of the transmitter is typically 5 dbm in normal mode and 10 dbm in boost mode. the tx output power can be set via register bits tx_pwr (register 0x05, phy_tx_pwr). the output power of the transmitter can be controlled down to -11 dbm db with 1 db resolution. to meet the spectral requirements of the european 868.3 mhz band it is necessary to limit the tx power by appropriate setti ng of tx_pwr, gc_pa (register 0x05, phy_tx_pwr) and gc_tx_offs (register 0x16, tx_ctrl_0), see table 7-15 and table 7-16. 7.3.5 tx power ramping to optimize the output power spectral density (psd), individual transmitter blocks are enabled sequentially. a transmit action is started by either the rising edge of pin slp_tr or the command tx_start in register 0x02. one symbol period later the data transmission begins. during this time period, the pll settles to the frequency used for transmission. the pa is enabled prior to the data transmission start. this pa lead time can be adjusted with the value pa_lt in register 0x16 (rf_ctrl_0).the pa is always enabled at the lowest gain value corresponding to gc_pa=0. then the pa gain is increased automatically to the value set by gc_pa in register 0x16 (rf_ctrl_0). after transmission is completed, tx power rampi ng down is performed in an inverse order. the control signals associated with tx power ramping are shown in figure 7-9. in this example, the transmission is initiated with the rising edge of pin 11 (slp_tr). the radio transceiver state changes from pll_on to busy_tx. figure 7-9. tx power ramping example (o-qpsk 250 kbit/s mode) 0 6810 slp_tr state pll_on 2 12 14 16 18 length [s] 4 pa modulation 11 11 11 00 0 busy_tx pa_lt using an external rf front-end (refer to section 9.4) it may be required to adjust the startup time of the external pa relative to the internal building blocks to optimize the overall psd. this can be achieved using register bits pa_lt (register 0x16, rf_ctrl_0).
105 8168b-mcu wireless-02/09 AT86RF212 7.3.6 register description regis ter 0x16 (rf_ctrl_0) : this register contains control sig nals to configure the transmit path. table 7-10. register 0x16 (rf_ctrl_0) bit 7 6 5 4 name pa_lt[1] pa_lt[0] reserved reserved read/write r/w r/w r/w r/w reset value 0 0 1 1 bit 3 2 1 0 name reserved reserved gc_tx_offs[1] gc_tx_offs[0] read/write r r r/w r/w reset value 0 0 0 1 ? bit 7:6 ? pa_lt these register bits control the lead time of the pa enable signal relative to the tx data start, see figure 7-9. this allows to enable the pa 2, 4, 6 or 8 s before the transmit sign al starts. the pa enable signal can also be output at pin dig3/dig4 to provide a control signal for an external rf front-end, for details refer to section 9.4. table 7-11. pa enable time relative to the tx start register bits value pa enable lead time [ s] 0 2 1 4 2 6 pa_lt 3 8 setting pa_lt is only effective in trx_off, pll_on and tx_aret_on mode. ? bit 5:2 ? reserved ? bit 1:0 ? gc_tx_offs these register bits provide an offset between the tx power control word tx_pwr (register 0x05, phy_tx_pwr) and the actual tx power. this 2-bit word is added to the tx power control word before it is applied to the circuit block which adjusts the tx power. it can be used to compensate differences of the average tx power depending of the modulation format, see table 7-16 . table 7-12. tx power offset register bits value tx power offset [db] 0 -1 1 0 2 +1 gc_tx_offs 3 +2 register 0x05 (phy_tx_pwr) : this register controls the transmitter output power.
106 8168b-mcu wireless-02/09 AT86RF212 table 7-13. register 0x05 (phy_tx_pwr) bit 7 6 5 4 name pa_boost gc_pa[1] gc_pa[0] tx_pwr[4] read/write r/w r/w r/w r/w reset value 0 1 1 0 bit 3 2 1 0 name tx_pwr[3] tx_pwr[2] tx_pwr[1] tx_pwr[0] read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_boost this bit enables the pa boost mode where the tx output power is increased by approximately 5 db when pa_boost=1. in pa boost mode the pa linearity is decreased compared to the normal mode when pa_boost=0. this leads to higher spectral side lobes of the tx power spectrum and higher power of the harmonics. consequently, the higher tx power settings do not fulfill the regulatory requirements of the european 868.3 mhz band regarding spurious emissions in adjacent frequency bands (see etsi en 300 220, erc/rec 70-03, and erc/dec/(01)04). ? bit 6:5 ? gc_pa these register bits control the gain of the pa by changing its bias current. gc_pa needs to be set in trx_off mode only. it can be used to reduce the supply current in tx mode when a reduced tx power is sele cted with the tx_pwr control word. a reduced pa bias current causes lower rf gain and lowers the 1 db- compression point of the pa. hence, it is advisable to use a reduced bias current of the pa only in combination with lower values of tx_pwr. a reasonable combination of tx_pwr and gc_pa is shown in table 7-15. table 7-14. AT86RF212 pa gain reduction relati ve to the gain at gc_pa=3 register bits value pa gain [db] 0 -2.9 1 -1.3 2 -0.9 gc_pa 3 0 ? bit 4:0 ? tx_pwr these register bits control the transmitter output power. the value of tx_pwr describes the power reduction relative to the maximum output power. the value gc_tx=0 provides the maximum output power. the resolution is 1 db per step. since tx_pwr adjusts the gain in the tx path prior to the pa, the pa bias setting is not optimal for increased values of tx_pwr regarding pa efficiency. pa power efficiency can be improved when pa bias is reduced (decreased gc_pa value) along with the tx power setting (increased tx_pwr value). a recommended combination of tx power control (tx_pwr), pa bias control (gc_pa) and pa boost mode (pa_boost) is listed in table 7-15. it is a recommended mapping of intended tx pow er to the 8-bit word in register 0x05. the value of tx_pwr shall be within the range of 0 to 12 to guarantee the transmit signal quality.
107 8168b-mcu wireless-02/09 AT86RF212 table 7-15. recommended mapping of tx power, frequency band, and phy_tx_pwr (register 0x05) phy_tx_pwr (register 0x05) 868.3 mhz european band phy modes: bpsk-20, oqpsk-sin-rc-{100,200,400} tx power [dbm] 915 mhz north american band phy modes: bpsk-40, oqpsk-sin- {250,500,1000} eu1 eu2 780 mhz chinese band phy modes: oqpsk-rc- {250,500,1000} 10 0xc0 9 0xa1 8 0x81 note 1 7 0x82 6 0x83 5 0x60 note 2 0xe7 0xe7 4 0x61 0xe8 note 4 0xe8 3 0x41 0xe9 0xe9 2 0x42 0x63 0xea 0xea 1 0x22 0x64 0xcb 0xca 0 0x23 0x65 note 4 0xab 0xaa -1 0x02 0x66 0xac 0xab -2 0x03 0x46 0xad 0x45 -3 0x04 0x26 0x48 0x25 -4 0x05 0x05 0x27 0x03 -5 0x06 0x06 0x06 0x04 -6 0x07 0x07 0x07 0x05 -7 0x08 0x08 0x08 0x06 -8 0x09 0x09 0x09 0x07 -9 0x0a 0x0a 0x0a 0x08 -10 0x0b 0x0b 0x0b 0x09 -11 0x0c note 3 0x0c note 5 0x0c note 5 0x0a note 1: power settings can be used with bpsk 40 kbit/s mode and o-qpsk 250 kbit/s mode. it is recommended to limit the maximum output power of the o-qpsk 500/1000 kbit/s modes because these modes are more sensitive to nonlinearities than the 250 kbit/s mode with larger spreading. note 2: power settings can be used with bpsk 40 kbit/s mode and o-qpsk 250/500 kbit/s modes. note 3: power settings can be used with all modes. note 4: power settings can be used with bpsk 20 kbit/s mode. spectral side lobes remain < -40dbm. note 5: power settings can be used with both bpsk 20 kbit/s mode and o-qpsk 100/200/400 kbit/s modes. spectral side lobes remain < -40 dbm.
108 8168b-mcu wireless-02/09 AT86RF212 the north american mapping table is optimized for lowest supply current. the more relaxed spectral side lobe requirements of the ieee 802.15.4 standard are fulfilled. the eu1 and eu2 mapping tables take into account that linearity is needed to keep the out-of-band spurious emissions below the etsi requirements. the map eu1 takes more supply current than the north american map and uses the normal (linearized) pa mode to provide m edium output power up to -1 dbm for o-qpsk 100/200/400 kbit/s modes and 2 db m for bpsk 20 kbit/s mode. the map eu2 uses the boost mode to provide higher tx power levels at the expense of higher supply current. as a result, the maximum tx power is 3 dbm for o-qpsk with 100/200/400 kbit/s and 5 dbm for bpsk with 20 kbit/s. the chinese mapping table takes into account that spectral side lobes must remain < -36 dbm according to the requirements defined by the ra dio management of p.r. of china in the technical requirements for micr opower (short distance) radio equipment. values of table 7-15 are based on a mode dependent setting of gc_tx_offs (re gister 0x16, rf_ctrl_0), which is shown in table 7-16. table 7-16. mode-dependent setting of gc_tx_offs mode bpsk o-qpsk gc_tx_offs 3 2 figure 7-10. supply current for o-qpsk modulation depending on tx power setting 10 12 14 16 18 20 22 24 26 -11-9-7-5-3-1 1 3 5 7 911 tx power [dbm] supply current [ma] north america eu1 eu2 china
109 8168b-mcu wireless-02/09 AT86RF212 7.4 frame buffer the AT86RF212 contains a 128 byte dual port sram. one port is connected to the spi interface, the other one to the internal transmitter and receiver modules. for data communication, both ports are independent and simultaneously accessible. the frame buffer utilizes the sram addres s space 0x00 to 0x7f for rx and tx operation of the radio transceiver and can keep a single i eee 802.15.4 rx or a single tx frame of maximum length at a time. frame buffer access modes are described in section 4.3.2. frame buffer access confli cts are indicated by an underrun interrupt irq_6 (trx_ur). note that this interrupt also occurs on the attempt to writ e frames longer than 127 octets to the frame buffer (overflow). in this case, the content of the frame buffer is undefined. frame buffer access is only possible if the digital voltage regulator is turned on. this is valid in all device states except in sleep state. an access in p_on state is possible once pin 17 (clkm) provides the 1 mhz master clock. 7.4.1 data management data in frame buffer (received data or data to be transmitted) can be changed by: ? frame buffer or sram write access over spi ? receiving a new frame in busy_rx or busy_rx_aack state ? a change into sleep state ? a reset by default, there is no protection of the fram e buffer against overwriting. therefore, if a frame is received during frame buffer read access of a previously received frame, interrupt irq_6 (trx_ur) is issued and t he stored data might be overwritten. even so, the old frame data can be read, if the spi data rate is higher than the effective over air data rate. for a data rate of 250 kbit/s, a minimum spi clock rate of 1 mhz is recommended. finally the microcontroller should check the transferred frame data integrity by an fcs check. to protect the frame buffer content against being overwritten by newly incoming frames the radio transceiver state should be changed to pll_on state after reception. this can be achieved by writing the command pll_on to register bits trx_cmd (register 0x02, trx_state) while or immediately after receiving the frame. alternatively, dynamic frame buffer protecti on can be used to protect received frames against overwriting, for details refer to section 9.7. both pro cedures do not protect the fr ame buffer from overwriting by the microcontroller. in extended operating mode du ring tx_aret operation, see 5.2.4, the radio transceive r switches to receive state, if an acknowledgement of a previously transmitted frame was requested. during this period, re ceived frames are evaluated but not stored in the frame buffer. this allows the radi o transceiver to wait for an acknowledgement frame and retry the frame transmission without writing the frame again. a radio transceiver state change, except a transition to sleep state or a reset, does not affect the frame buffer content. if the radio transceiver is taken into sleep, the frame buffer is powered off and the stored data get lost.
110 8168b-mcu wireless-02/09 AT86RF212 7.4.2 frame content the AT86RF212 supports an ieee 802.15.4 compliant frame format as shown in figure 7-11. figure 7-11. AT86RF212 frame structure preamble sequence sfd phr payload lqi fcs 0 4 5 6 n + 3 n + 5 n + 6 frame access shr not accessible phy generated length [octets] duration 4 octets 1 n octets ( n <= 128) 3 octets frame buffer content / frame write access (1) ed rx_status n + 7 n + 8 frame read access sfd_value note: 1. writing fcs can be omitted, if tx_auto_crc_on = 1 (register 0x04, txr_ctrl_1). a frame comprises two sections, the radio transceiver internally generated shr field and the user accessible part stored in the frame buffer. the shr contains the preamble and the sfd field. the variable frame section contains the phr and the psdu including the fcs, see section 6.3. to acce ss the data follow the procedures described in section 4.3.2. the frame l ength information (phr field) and the psdu are stored in the frame buffer. during frame reception, the link quality indicator (lqi) value, the energy detection (ed) value, and the status information (rx_stat us) of a received frame are additionally stored, see sections 6.8, 6.5, and 4.3.2, respectively. the radio transceiver appends these valu es to the frame data during frame buffer read access. if the sram read access is used to read an rx frame, the frame length field (phr) can be accessed at address 0. the shr (except the sfd value used to generate the shr) cannot be read by the microcontroller. for frame transmission, the phr and the psdu need to be stored in the frame buffer. the maximum frame buffer size supported by the radio transceiver is 128 bytes. if the tx_auto_crc_on bit is set in register 0x05 (phy_tx_pwr), the fcs field of the psdu is replaced by the automatically calculated fcs during frame transmission. there is no need to write the fcs field when using the automatic fcs generation. to manipulate individual bytes of the frame buffer a sram write access can be used instead. for non ieee 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte (frame length field + 1 byte of data). 7.4.3 interrupt handling access conflicts may occur when reading and writing data simultaneously at the independent ports of the frame buffer, tx/rx bbp and spi. these ports have their own address counter that points to the frame buffer?s current address. access violations occurs during concurrent frame buffer read or write accesses, when the spi port?s address counter value becomes greater than or equal to that of tx/rx bbp port.
111 8168b-mcu wireless-02/09 AT86RF212 while receiving a frame, first the data need to be stored in the frame buffer before reading it. this can be ensured by accessing the frame buffer at least 8 symbols (bpsk) or 2 symbols (o-qpsk) after interr upt irq_2 (rx_start). when reading the frame data continuously, the spi data rate shall be lower than the current trx bit rate to ensure no underrun interrupt occurs. to avoid access conflicts and to simplify the frame buffer read access, frame buffer empty indication may be used, for details refer to section 9.6. duri ng transmission, an access violation occurs on frame buffer write access, when the spi port?s address counter value becomes less than or equal to that of tx bbp port. both access violations may cause data corruption and are indicated by irq_6 (trx_ur) interrupt when using the frame buffer access mode. note that access violations are not indicated when using the sram access mode. when writing data to the frame buffer during frame transmission, the spi data rate shall be higher than the phy data rate avoiding underrun. the first byte of the psdu data must be available in the frame buffer before sfd transmission is complete, which takes 41 symbol periods for bpsk (1 sym bol pa ramp up + 40 symbols shr) and 11 symbol periods for o-qpsk (1 symbol pa ra mp up + 10 symbols shr) from the rising edge of slp_tr pin (see figure 5-2). notes ? interrupt irq_6 (trx_ur) is valid 1 octe t after irq_2 (rx_star t). the occurrence of the interrupt shall be ignored when reading the first byte of the frame buffer between the first and second octet after the rx_start interrupt. ? if a frame buffer read access is not finished until a new frame is received, a trx_ur interrupt occurs. nevertheless, the old frame data can be read if the spi data rate is higher than the effective phy data rate. a minimum spi clock rate of 1 mhz is recommended in this case. finally, the microcontroller should check the integrity of the transferred frame data by calculating the fcs. 7.5 voltage regulators (avreg, dvreg) the main features of the voltage regulator blocks are: ? bandgap stabilized 1.8 v supply for analog and digital domain ? low dropout (ldo) voltage regulator ? configurable for usage of external voltage regulator 7.5.1 overview the internal voltage regulators supply a stabilized voltage to the AT86RF212. the avreg provides the regulated 1.8 v supply voltage for the analog section and the dvreg supplies the 1.8 v supply voltage for the digital section. a simplified schematic of the internal analog voltage regulator is shown in figure 7-12.
112 8168b-mcu wireless-02/09 AT86RF212 figure 7-12. simplified schematic of avreg bandgap voltage reference 1.25v avdd evdd a simplified schematic of the internal digital voltage regulator is shown in figure 7-13. figure 7-13. simplified schematic of dvreg bandgap voltage reference 1.25v dvdd devdd bias voltage regulator low power voltage regulator digital voltage regulator the block ?low power voltage regulator? within the ?digital voltage regulator? maintains the dvdd supply voltage when the voltage regulator is disabled, which is the case during sleep mode (refer to figure 7-13). the dvdd voltage drops down to 1.5 v (typical ) if the AT86RF212 is in sleep mode, a ll configuration register values are stored. the low power voltage regulator is always enabled. therefore its bias current contributes to the leakage current in sleep mode of about 100 na (typ.). the voltage regulators (avreg, dvreg) require bypass capacitors for stable operation. the value of the bypass capacitors determine the settling time of the voltage regulators. the bypass capacitors shall be placed as close as possible to the pins and shall be connected to ground with the shortest possible traces (see table 3-1). 7.5.2 configuration the voltage regulators can be configured by the register 0x10 (vreg_ctrl).
113 8168b-mcu wireless-02/09 AT86RF212 it is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external voltage supply. for this configuration, the internal regulators need to be switched off by setting the register bits to the values avreg_ext = 1 and dvreg_ext = 1. a regulated external supply voltage of 1.8 v needs to be connected to the pins 13, 14 (dvdd) and pin 29 (avdd). when turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF212. 7.5.3 data interpretation the status bits avdd_ok = 1 and dvdd_ok = 1 of register 0x10 (vreg_ctrl) indicate an enabled and stable internal supply voltage. reading value 0 indicates a disabled voltage regulator or the internal supply voltage is not settled to the final value. setting avreg_ext=1 and dvreg_ext=1 forces the signals avdd_ok and dvdd_ok to 1. 7.5.4 register description regis ter 0x10 (vreg_ctrl) : this register controls the use of the voltage regulators and indicates the status of these. table 7-17. register 0x10 (vreg_ctrl) bit 7 6 5 4 name avreg_ext avdd_ok reserved reserved read/write r/w r r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name dvreg_ext dvdd_ok reserved reserved read/write r/w r r/w r/w reset value 0 0 0 0 ? bit 7 ? avreg_ext if set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8 v supply for the analog building blocks. table 7-18. regulated voltage supply control for analog building blocks register bit value description 0 internal voltage regulator enabled, analog section avreg_ext 1 internal voltage regulator disabled, use external regulated 1.8 v supply volt age for the analog section ? bit 6 ? avdd_ok this register bit indicates if the internal 1.8 v regulated voltage supply avdd has settled. the bit is set to logic high, if avreg_ext = 1. table 7-19. regulated voltage supply control for analog building blocks register bit value description 0 analog voltage regulator disabled or supply voltage not stable avdd_ok 1 analog supply voltage has settled
114 8168b-mcu wireless-02/09 AT86RF212 ? bit 5:4 ? reserved ? bit 3 ? dvreg_ext if set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8 v supply for the digital building blocks. table 7-20. regulated voltage supply control for digital building blocks register bit value description 0 internal voltage regulator enabled, digital section dvreg_ext 1 internal voltage regulator disabled, use external regulated 1.8 v supply volta ge for the digital section ? bit 2 ? dvdd_ok this register bit indicates if the internal 1.8 v regulated voltage supply dvdd has settled. the bit is set to logic high, if dvreg_ext = 1. table 7-21. regulated voltage supply control for digital building blocks register bit value description 0 digital voltage regulator disabled or supply voltage not stable dvdd_ok 1 digital supply voltage has settled note ? while the reset value of this bit is 0, any practical access to the register is only possible when dvreg is active. so this bi t is normally always read out as 1. ? bit 1:0 ? reserved register 0x0c (trx_ctrl_2) : this register controls the trx behavior. table 7-22. register 0x0c (trx_ctrl_2) bit 7 6 5 4 name rx_safe_mode trx_off_avdd_en oqpsk_scram_en oqpsk_sub1_rc_en read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name bpsk_oqpsk sub_mode oqpsk_data_rate oqpsk_data_rate read/write r/w r/w r/w r/w reset value 0 1 0 0 ? bit 6 ? trx_off_avdd_en if this register bit is set, the analog voltage regulator is turned on (kept on) during trx_off, enabling faster rx/tx turn on time . this is especially usefull for a short stopover in trx_off state. the recharge time for capacitances is avoided in this case. the current consumption increases by typical 100 a.
115 8168b-mcu wireless-02/09 AT86RF212 7.6 battery monitor (batmon) the main features of the battery monitor are: ? configurable voltage threshold range: 1.7 v to 3.675 v ? generation of an interrupt when supply voltage drops below the threshold ? current state can be monitored in a register bit 7.6.1 overview the battery monitor (batmon) detects and indicates a low supply voltage of the external supply voltage at pin 28 (evdd). this is done by comparing the voltage on the external supply pin 28 (evdd) with a c onfigurable internal threshold voltage. a simplified schematic of the batmon with the most important input and output signals is shown in figure 7-14. figure 7-14. simplified schematic of batmon batmon_hr batmon_vth 4 evdd threshold voltage batmon_ok ?1? batmon_irq for input-to-output mapping see control register 0x11 (batmon) dac + - d q clear 7.6.2 configuration the batmon can be configured using the register 0x11 (batmon). register subfield batmon_vth sets the threshold voltage. it is configurable with a resolution of 75 mv in the upper voltage range (batmon_hr = 1) and with a resolution of 50 mv in the lower voltage range (batmon_hr = 0), for details refer to register 0x11 (batmon). 7.6.3 data interpretation the register bit batmon_ok of register 0x11 (batmon) represents the current value of the supply voltage: ? if batmon_ok = 0, the supply voltage is lower than the threshold voltage ? if batmon_ok = 1, the supply voltage is higher than the threshold voltage after setting a new threshold, the value batmon_ok should be read out to verify the current supply voltage value. note, the battery monitor is inactive during p_on and sleep states, see status register 0x01 (trx_status). 7.6.4 interrupt handling a supply voltage drop below the configured threshold value is indicated by interrupt irq_7 (bat_low), see section 4.7. note that the interrupt is issued only if batmon_ ok changes from 1 to 0.
116 8168b-mcu wireless-02/09 AT86RF212 no interrupt is generated when: ? the supply voltage is below the default 1.8 v threshold at power up (batmon_ok was never 1), or ? a new threshold is set, which is still above the current supply voltage (batmon_ok remains 0). when the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. to avoid this: ? disable the irq_7 (bat_low ) in register 0x0e (irq_mask) and treat the battery as empty, or ? set a lower threshold value. 7.6.5 register description r egister 0x11 (batmon) : this register configures the battery monitor to compare the supply voltage evdd at pin 28 to the threshold. additionally, the supply voltage status at pin 28 (evdd) can be read from register bit batmon_ok according to the actual batmon settings. table 7-23. register 0x11 (batmon) bit 7 6 5 4 name reserved reserved batmon_ok batmon_hr read/write r r/w r r/w reset value 0 0 0 0 bit 3 2 1 0 name batmon_vth[3] batmon_vth[2] batmon_vth[1] batmon_vth[0] read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 7:6 ? reserved ? bit 5 ? batmon_ok the register bit batmon_ok indicates the level of the external supply voltage with respect to the programmed threshold batmon_vth. table 7-24. battery monitor status register bit value description 0 the battery voltage is below the threshold. batmon_ok 1 the battery voltage is above the threshold. ? bit 4 ? batmon_hr the register bit batmon_hr sets the range and resolution of the battery monitor. table 7-25. battery monitor range selection register bit value description 0 enables the low range, see batmon_vth batmon_hr 1 enables the high range, see batmon_vth
117 8168b-mcu wireless-02/09 AT86RF212 ? bit 3:0 ? batmon_vth the threshold values for the battery monitor are set by register bits batmon_vth: table 7-26. battery monitor threshold voltages value batmon_vth[3:0] voltage [v] batmon_hr = 1 voltage [v] batmon_hr = 0 0x0 2.550 1.70 0x1 2.625 1.75 0x2 2.700 1.80 0x3 2.775 1.85 0x4 2.850 1.90 0x5 2.925 1.95 0x6 3.000 2.00 0x7 3.075 2.05 0x8 3.150 2.10 0x9 3.225 2.15 0xa 3.300 2.20 0xb 3.375 2.25 0xc 3.450 2.30 0xd 3.525 2.35 0xe 3.600 2.40 0xf 3.675 2.45 7.7 crystal oscillator (xosc) and clock output (clkm) the main features are: ? 16 mhz amplitude-controlled crystal oscillator ? fast settling time after leaving sleep state ? configurable trimming capacitance array ? configurable clock output (clkm) 7.7.1 overview the crystal oscillator generates the reference frequency for the AT86RF212. all other internally generated frequencies of the radio transceiver are derived from this frequency. therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency. the external components of the crystal oscillator should be selected carefully and the related board layout should be done with caution (see section 3). two o perating modes are supported. the recommended mode is the integrated oscillator setup as described in figure 7-15. alternatively, a reference frequency can be fed to the int ernal circuitry by using an external clock reference as shown in figure 7- 16. the xosc ope rating modes are configur able by register 0x12 (xosc_ctrl).
118 8168b-mcu wireless-02/09 AT86RF212 7.7.2 integrated oscillator setup using the internal oscillator, the oscillation frequency depends on the load capacitance between the crystal pins xtal1 and xtal2. the total load capacitance c l must be equal to the specified load capacitance of the crystal itself. it consists of the external capacitors cx and parasitic capacitances connected to the xtal nodes. figure 7-15 shows parasitic capacitances, such as pcb stray capacitances. figure 7-15. simplified xosc schematic with external components cx cx 16mhz xtal2 xtal1 evdd c trim c trim c pcb c pcb AT86RF212 pcb xtal_trim[3:0] evdd v dd xtal_trim[3:0] additional internal trimming capacitors c trim are available. values in the range from 0 pf to 4.5 pf with a 0.3 pf resolution are selectable using the bits xtal_trim of register 0x12 (xosc_ctrl). to calculate the total load capacitance, the following formula can be used, while c par represents the pin input capacitance, defined in table 2-2. c l = 0.5 ? (cx + c trim + c par + c pcb ) the trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by ex ternal components tolerances. note that the oscillation frequency can only be reduced by increasing the trimming capacitance. the frequency deviation caused by one step of c trim decreases with increasing crystal load capacitor values. an amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal types. enabling the crystal oscillator in p_on state and after leaving sleep state caus es a slightly higher current during the amplitude build-up phase to guarantee a short start-up time. at stable operation, the current is reduced to the amount necessary for a robust operation. this also keeps the drive level of the crystal low. generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external component variations or by variations of board and circuit parasitics. on the other hand, a larger crystal load capacitance results in a longer start- up time and a higher steady state current consumption.
119 8168b-mcu wireless-02/09 AT86RF212 7.7.3 external reference frequency setup when using an external reference frequency, the signal must be connected to pin 26 (xtal1) as indicated in figure 7-16 and the register bits xtal_mode (register 0x12, xosc _ctrl) need to be set to the external oscillator mode. the oscillation peak-to-peak amplitude shall be between 100 mv and 500 mv, the optimum range is between 400 mv and 500 mv. pin 25 (xtal2) should not be wired. note that the quality of the external reference (i.e. pha se noise) determines the system performance. figure 7-16. setup for using an external frequency reference xtal2 xtal1 AT86RF212 pcb 16 mhz 7.7.4 master clock signal output (clkm) the generated reference clock signal can be fed into a microcontroller using pin 17 (clkm). the internal 16 mhz raw clock can be divided by an internal prescaler. thus, clock frequencies of 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, 250 khz, or the current shr symbol rate frequency can be supplied by pin clkm. the clkm frequency and pin driver streng th is configurable using register 0x03 (trx_ctrl_0). there are two mode s how a clkm frequency change gets effective. if clkm_sha_sel = 0, changing the register bits clkm_ctrl (register 0x03, trx_ctrl_0) immediately affect s the clkm clock rate. otherwise (clkm_sha_sel = 1) the new clock rate is supplied when leaving the sleep state the next time. to reduce power consumption and spurious em issions, it is recommended to turn off the clkm clock when not in use or to reduce its driver strength to a minimum, refer to section 2.2.2. clkm reset behavior during reset procedure, see section 5.1.4.5, register bits clkm_ctrl are shadowed. although th e clock setting of clkm remains after reset, a read access to register bits clkm_ctrl delivers the reset value 1. for t hat reason it is recommended to write the previous configuration, before reset, to regi ster bits clkm_ctrl, after reset, to align the radio transceiver behavior and register configuration. otherwise the clkm clock rate is set back to the reset value (1 mhz) after the next sleep cycle. for example, if the clkm clock rate is configured to 16 mhz the clkm clock rate remains at 16 mhz after a reset, however the register bits clkm_ctrl are set back to 1. since clkm_sha_sel reset value is 1, the clkm clock rate changes to 1 mhz after the next sleep cycle if the clkm_ctrl setting is not updated. 7.7.5 clock jitter AT86RF212 provides receiver sensitivities up to -110 dbm. detection of such small rf signals requires very clean scenarios with respect to noise and interference. harmonics of digital signals may degrade the performance if they interfere with the wanted rf
120 8168b-mcu wireless-02/09 AT86RF212 signal. a small clock jitter of digital signals can spread harmonics over a wider frequency range thus reducing the power of ce rtain spectral lines. AT86RF212 provides such a clock jitter as an optional feature. the jitter module is working for the receiver part and all i/o signals, e.g. clkm, if enabl ed. the transmitter part and rf frequency generation are not influenced. 7.7.6 register description regis ter 0x03 (trx_ctrl_0) : table 7-27. register 0x03 (trx_ctrl_0) bit 7 6 5 4 name pad_io pad_io pad_io_clkm[1] pad_io_clkm[0] read/write r/w r/w r/w r/w reset value 0 0 0 1 bit 3 2 1 0 name clkm_sha_sel clkm_ctrl[2] clkm_ctrl[1] clkm_ctrl[0] read/write r/w r/w r/w r/w reset value 1 0 0 1 the trx_ctrl_0 register controls the drive current of the digital outputs and the clkm clock rate. it is recommended using the lowest value for the drive current to reduce the current consumption and the emission of signal harmonics. ? bit 7:6 ? pad_io refer to section 2.2.2.3. ? bit 5:6 ? pad_io_clkm these register bits set the output driver strength of pin clkm. it is recommended reducing the driver strength to 2 ma (pad _io_clkm = 0) if possible. this reduces power consumption and spurious emissions. table 7-28. clkm driver strength register bits value description 0 2 ma 1 4 ma 2 6 ma pad_io_clkm 3 8 ma ? bit 3 ? clkm_sha_sel the register bit clkm_sha_sel defines whether a new clock rate, defined by clkm_ctrl, is set immediately or get s effective after the next sleep cycle. table 7-29. clkm clock rate update scheme register bit value description 0 clkm clock rate change appears immediately clkm_sha_sel 1 clkm clock rate change appears after sleep cycle ? bit 2:0 ? clkm_ctrl these register bits set clock rate of pin 17 (clkm).
121 8168b-mcu wireless-02/09 AT86RF212 table 7-30. clock rate setting at pin clkm register bits value description 0 no clock at pin 17 (clkm), pin set to logic low 1 1 mhz 2 2 mhz 3 4 mhz 4 8 mhz 5 16 mhz 6 250 khz ieee 802.15.4 symbol rate frequencies bpsk_oqpsk (1) sub_mode (1) frequency 0 0 20 khz 0 1 40 khz 1 0 25 khz clkm_ctrl 7 1 1 62.5 khz note: 1. refer to section 7.1.5 register 0x12 (xosc_ctrl) : the register xosc_ctrl configures the crystal oscillator. table 7-31. register 0x12 (xosc_ctrl) bit 7 6 5 4 name xtal_mode[3] xtal_mode[2] xtal_mode[1] xtal_mode[0] read/write r/w r/w r/w r/w reset value 1 1 1 1 bit 3 2 1 0 name xtal_trim[3] xtal_trim[2] xtal_trim[1] xtal_trim[0] read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:4 ? xtal_mode these register bits set the operating mode of the crystal oscillator, see table 7-32. table 7-32. crystal oscillator operating mode register bits value description 0x4 internal crystal oscillator disabled, use external reference frequency 0xf internal crystal oscillator enabled xtal_mode other reserved ? bit 3:0 ? xtal_trim the register bits xtal_trim control the two internal capacitance arrays connected to pins xtal1 and xtal2. a capacitance value in the range from 0 pf to 4.5 pf is selectable with a resolution of 0.3 pf.
122 8168b-mcu wireless-02/09 AT86RF212 table 7-33. crystal oscillator trimming capacitors register bits value description 0x0 0.0 pf 0x1 0.3 pf ? 0xf 4.5 pf xtal_trim other reserved register 0x0a (rx_ctrl) : the register rx_ctrl conf igures the clock jitter. table 7-34. register 0x0a (rx_ctrl) bit 7 6 5 4 name reserved reserved jcm_en reserved read/write r/w r/w r/w r/w reset value 1 0 0 1 bit 3 2 1 0 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 1 1 1 ? bit 7:6 ? reserved ? bit 5 ? jcm_en if this bit is set, the jitter module is enabled. ? bit 4:0 ? reserved 7.8 frequency synthesizer (pll) the main pll features are: ? generate rx/tx frequencies for all supported channels ? autonomous calibration loops for stable operation within the operating range ? two pll interrupts for status indication ? fast pll settling to support frequency hopping 7.8.1 overview the pll generates the rf frequencies for the AT86RF212. during receive and transmit operations the frequency synthesizer operates as a local oscillator. the frequency synthesizer is implemented as a fractional -n pll with analog compensation of the fractional phase error. the vco is running at double of the rf frequency. two calibration loops ensure correct pll functionality within the specified operating limits.
123 8168b-mcu wireless-02/09 AT86RF212 7.8.2 rf channel selection the pll is designed to support ? one channel in the european srd band from 863 to 870 mhz at 868.3 mhz according to ieee 802.15.4 (channel k =0) ? 10 channels in the north american ism band from 902 to 928 mhz with a channel spacing of 2 mhz according to ieee 802.15.4. the center fr equency of these channels is defined as f c = 906 + 2 ? ( k -1) [mhz] where k is the channel number ranging from 1 to 10. ? 4 channels in the chinese wpan band from 779 to 787 mhz with a channel spacing of 2 mhz according to ieee p802.15.4c. c enter frequencies are 780, 782, 784, and 786 mhz. additionally, the pll supports all frequen cies from 769 to 935 mhz with 1 mhz frequency spacing and 3 bands with 100 khz spacing from 769 to 794.5 mhz, 857 to 882.5 mhz, and 903 to 928.5 mhz. the frequency is selected by register s 0x13 (cc_number, cc_ctrl_0[7:0]) and 0x14 (cc_band, cc_ctrl_1[2:0]). table 7-35 shows the settings of the registers cc_ct rl_0 and cc_ctrl_1. table 7-35. frequency bands and numbers cc_band, cc_ctrl_1 cc_number, cc_ctrl_0 description 0 not used european and north american channels according to ieee 802.15.4; frequency selected by register bits channel (register 0x08, phy_cc_cca), refer to section 7.8.6 1 0 ? 255 769 ? 794.5 mhz; f c = 769 + 0.1 * cc_ctrl_0 [mhz] 2 0 ? 255 857 ? 882.5 mhz; f c = 857 + 0.1 * cc_ctrl_0 [mhz] 3 0 ? 255 903 ? 928.5 mhz; f c = 903 + 0.1 * cc_ctrl_0 [mhz] 4 0 ? 94 769 ? 863 mhz; f c = 769 + cc_ctrl_0 [mhz] 5 0 ? 102 833 ? 935 mhz; f c = 833 + cc_ctrl_0 [mhz] 6, 7 0 ? 255 reserved the pll frequency in pll_on and receive st ates is 1 mhz below the pll frequency in transmit states. 7.8.3 pll settling time and frequency agility when the pll is enabled during state transit ion from trx_off to pll_on, the settling time is typically t tr4 = 110 s (50 s plus 60 s settling time of the analog voltage regulator avreg), including pll self calibration, refer to table 5-1 and section 7.8.4. the lockin g of the pll is indicated with the interrupt irq_0 (pll_lock). switching between channels within a frequenc y band in pll_on or rx_on states is typically done within t tr20 = 11 s. this makes the radio transceiver highly suitable for frequency hopping applications. in pll_on state and receive states the p ll settles to the receive frequency.
124 8168b-mcu wireless-02/09 AT86RF212 when starting the transmit procedure the pll frequency is changed to the transmit frequency within a period of t tr23 = 16 s before starting t he transmission. after the transmission the pll settles back to the receive frequency within a period of t tr24 = 32 s. these frequency changes do not generat e the interrupt irq_0 (pll_lock) or irq_1 (pll_unlock). 7.8.4 calibration loops due to variation of temperature, supp ly voltage, and center frequency, the vco characteristics may vary. to ensure a stable operation, two automa ted control loops are implemented: center frequency and delay cell calibration. both cali bration loops are initiated automatically when the pll is enabled during state transition from trx_off to pll_on or rx_on. additionally, both calibration loops are initiated when the pll changes to a different frequency setting. if the pll operates for a long time on the same channel or the operating temperature changes significantly, the calibration loops should be initiated manually. the recommended calibration interval is 5 minutes or less. both calibration loops can be initiated manually by spi command. to start the calibration the device should be in state pll_on. the center frequency calibration can be initiated by setting pll_cf_start = 1 (register 0x1a, pll_cf). center frequency calibration generates (if enabled) a pll_unlock interrupt. the calibration lo op is completed when the pll_lock interrupt occurs (if enabled). the duration of the center frequency calibration loop depends on the difference between the current cf value and the final cf value. during the calibration the cf value is incremented or decremented. each step takes 8 s. the minimum time is 8 s, the maximum time is 270 s. the recommended procedure to start the center frequency calibration is to read the register 0x1a (pll_cf), to set the pll_cf_start register bit to 1, and to write the value back to the register. the delay cell calibration can be initiat ed by setting the bit pll_dcu_start of register 0x1b (pll_dcu) to 1. the delay time of the programmable delay unit is adjusted to the correct value. the calibration works as successive approximation and is independent of the values in the regist er 0x1b (pll_dcu). the duration of the calibration is 10 s. during both calibration processes no correct re ceive or transmit operation is possible. the recommended state for the calibration is therefore pll_on, but calibration is not blocked at receive or transmit states. both calibrations can be executed concurrently. 7.8.5 interrupt handling two different interrupts indicate the pll st atus. irq_0 (pll_lock) indicates that the pll has locked. irq_1 (pll_unlock) interrupt indicates an unexpected unlock condition. a pll_lock interrupt clears any preceding pll_unlock interrupt automatically and vice versa. a pll_lock interrupt occurs in the following situations: ? state change from trx_off to pll_on / rx_on ? frequency setting change in states pll_on / rx_on ? a manually started center frequency calibration has been completed
125 8168b-mcu wireless-02/09 AT86RF212 all other pll_lock interrupt events indicate that the pll locked again after a prior unlock happened. a pll_unlock interrupt occurs in the following situations: ? a manually initiated center frequency ca libration in states pll_on / (rx_on) ? frequency setting change in states pll_on / rx_on pll_lock and pll_unlock affect the behavior of the transceiver: in the states busy_tx and busy_tx_are t, the transmission is stopped and the transceiver returns into state pll_on. during busy_rx and busy_rx_aack the transceiver returns to state rx_on and rx _aack_on, respectively, once the pll has locked. 7.8.6 register description regis ter 0x08 (phy_cc_cca) : the register phy_cc_cca contains register bits to set the channel center frequency according to ieee 802.15.4 for the european a nd north american band. a write access to the register bits channel sets t he channel number; a read access shows the current channel number. it is necessary to set register bits cc_band (register 0x14, cc_ctrl_1) to 0 in order to enable the above described channel selection, see table 7-35. table 7-36. register 0x08 (phy_cc_cca) bit 7 6 5 4 name cca_request cca_mode cca_mode channel[4] read/write w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name channel[3] channel[2] channel[1] channel[0] read/write r/w r/w r/w r/w reset value 0 1 0 1 table 7-37. channel assignment according to ieee 802.15.4 register bits value channel number k frequency [mhz] 0x00 0 868.3 0x01 1 906 0x02 2 908 0x03 3 910 0x04 4 912 0x05 5 914 0x06 6 916 0x07 7 918 0x08 8 920 0x09 9 922 channel 0x0a 10 924
126 8168b-mcu wireless-02/09 AT86RF212 register bits value channel number k frequency [mhz] 0x0b?0x1f reserved register 0x13 (cc_ctrl_0) : this register controls the frequency selection, if the selection by channel number is not used. table 7-38. register 0x13 (cc_ctrl_0) bit 7 6 5 4 3 2 1 0 name cc_number[7:0] read/write r/w reset value 0 0 0 0 0 0 0 0 register 0x14 (cc_ctrl_1) : this register selects the frequency band. table 7-39. register 0x14 (cc_ctrl_1) bit 7 6 5 4 name reserved reserved reserved reserved read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name reserved cc_band[2] cc_band[1] cc_band[0] read/write r r/w r/w r/w reset value 0 0 0 0 the functionality of the registers cc_ctrl_0 and cc_ctrl_1 is documented in table 7-35. register 0x1a (pll_cf) : this register controls the operation of the center frequency calibration loop. table 7-40. register 0x1a (pll_cf) bit 7 6 5 4 name pll_cf_start reserved reserved pll_cf[4] read/write r/w r/w r/w r/w reset value 0 1 0 0 bit 3 2 1 0 name pll_cf[3] pll_cf[2] pll_cf[1] pll_cf[0] read/write r/w r/w r/w r/w reset value 1 0 0 0
127 8168b-mcu wireless-02/09 AT86RF212 ? bit 7 ? pll_cf_start pll_cf_start = 1 initiates the center frequency calibration. when the calibration cycle has finished after at most 25 s the register bit pll_cf_start is reset to 0. ? bit 6:5 these bits are reserved and must always be written back using the reset values. ? bit 4:0 ? pll_cf bits 4:0 represent the current cf state of the pll. in order to assure the shortest possible calibration time they should not be changed when starting center frequency tuning. register 0x1b (pll_dcu) : this register controls the operatio n of the delay cell calibration loop. table 7-41. register 0x1b (pll_dcu) bit 7 6 5 4 name pll_dcu_start reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 1 0 0 bit 3 2 1 0 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pll_dcu_start pll_dcu_start = 1 initiates the delay cell calibration. the calibration cycle is completed after 10 s, and the register bit p ll_dcu_start is set to 0. the register bit is cleared immediately after finishing the calibration. ? bit 6:0 ? reserved 7.9 automatic filter tuning (ftn) 7.9.1 overview the ftn is incorporated to compensate for temperature, supply voltage variations, and part-to-part variations of the radio transceiver. a calibration cycle is initiated automatically when entering the trx_off state from the sleep, reset or p_on states. although receiver and transmitter are very robust against these variations, it is recommended to initiate the ftn manually, if the radio transceiver does not regularly use the sleep state. this applies in particular for the high data rate modes with higher sensitivity against variations. the recommended calibration interval is about 5 minutes. 7.9.2 register description r egister 0x18 (ftn_ctrl) : this register controls the operation of the filter tuning calibration loop.
128 8168b-mcu wireless-02/09 AT86RF212 table 7-42. register 0x18 (ftn_ctrl) bit 7 6 5 4 name ftn_start reserved reserved reserved read/write s r/w r/w r/w reset value 0 1 0 1 bit 3 2 1 0 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 1 0 0 0 ? bit 7 ? ftn_start ftn_start = 1 initiates the filter tuning ca libration loop. ones the calibration cycle has finished within a maximum time period of 25 s, the register bit is automatically reset to 0. ? bit 6:0 ? reserved
129 8168b-mcu wireless-02/09 AT86RF212 8 radio transceiver usage this section describes basic procedures to receive and transmit frames using the AT86RF212. 8.1 frame receive procedure a frame reception comprises of two actions: the transceiver listens for, receives and demodulates the frame to the frame buffer and signals the reception to the microcontroller. after or during that proce ss, the microcontroller can read the available frame data from the frame buffer via the spi interface. while being in state rx_on or rx_aack_ on, the radio transceiver searches for incoming frames on the selected channel. assuming the appropriate interrupts are enabled, a detection of an ieee 802.15.4-2006 compliant frame is indicated by interrupt irq_2 (rx_start). when the frame recept ion is completed, interrupt irq_3 (trx_end) is issued. different frame buffer read access scenarios are recommended for: ? non-time critical applications r ead access starts after irq_3 (trx_end) ? time-critical applications read access starts after irq_2 (rx_start) for non time critical operations, it is recommended to wait for interrupt irq_3 (trx_end) before starting a frame buffer read access. figure 8-1 illustrates the frame receive proce dure usin g irq_3 (trx_end). figure 8-1. transactions between AT86RF212 and microcontroller during receive AT86RF212 microcontroller irq issued (irq_2) read irq status, pin 24 (irq) deasserted irq issued (irq_3) read frame data (frame buffer access) read irq status, pin 24 (irq) deasserted critical protocol timing could require starting the frame buffer read access after interrupt irq_2 (rx_start). the first byte of the frame data can be read one octet time period after the irq_2 (rx_start) inte rrupt. the microcontroller must ensure to read slower than the frame is received. ot herwise, a frame buffer underrun occurs, irq_6 (trx_ur) is issued, and the frame data may be not valid. to avoid this, the frame buffer read access can be controlled by using a frame buffer empty indicator, refer to section 9.6.
130 8168b-mcu wireless-02/09 AT86RF212 8.2 frame transmit procedure a frame transmission comprises of two actions, a frame buffer write access and the transmission of the frame buffer content. both actions can be run in parallel if required by critical protocol timing. figure 8-2 illustrates the frame transmit pr o cedure, when writing and transmitting the frame consecutively. after a frame buffer write access, the frame transmission is initiated by asserting pin 11 (slp_tr) or writing command tx_start to register 0x02 (trx_state), while the radio transceiver is in state pll_on or tx_aret_on. the completion of the transaction is indicated by interrupt irq_3 (trx_end). figure 8-2. transaction between AT86RF212 and microcontroller during transmit AT86RF212 microcontroller write frame data (frame buffer access) write trx_cmd = tx_start, or assert pin 11 (slp_tr) irq_3 (trx_end) issued read irq_status register, pin 24 (irq) deasserted alternatively, a frame transmission can be started first, followed by the frame buffer write access (psdu data); refer to figure 8-3. this is applicable for time critical appli cations. initiating a transmission, either by assert ing pin 11 (slp_tr) or command tx_start to register bits trx_cmd (register 0x02, trx_state), the radio transceiver starts transmitting the shr, which is internally generated. front end initialization takes one symbol per iod for pll settling and pa ramp up. shr transmission takes another 40 symbol periods for bpsk or 10 symbol periods for o- qpsk. the phr must be available in the frame buffe r before this time elapses. furthermore, the spi data rate must be higher than the phy data rate selected by register bits oqpsk_data_rate (registe r 0x0c, trx_ctrl_2) to avoid a frame buffer underrun, indicated by irq_6 (trx_ur), refer to section 7.1.4. figure 8-3. time optimized frame transmit procedure irq_3 (trx_end) issued write frame data (frame buffer access) write trx_cmd = tx_start, or assert pin 11 (slp_tr) AT86RF212 microcontroller read irq_status register, pin 24 (irq) deasserted
131 8168b-mcu wireless-02/09 AT86RF212 9 extended feature set 9.1 security module (aes) the security module (aes) is characterized by: ? hardware accelerated encryption and decryption ? compatible with aes-128 standard (1 28 bit key and data block size) ? ecb (encryption/decryption) mode and cbc (encryption) mode support ? stand-alone operation, independent of other blocks 9.1.1 overview the security module is ba sed on an aes-128 co re according to fips197 standard, refer to [7]. the security module is independent from other building blocks of the AT86RF212. encryption and decryption can be performed in parallel to a frame transmission or reception. controlling the security block is implemented as an sram access to address space 0x82 to 0x94. a fast sram access mode allows simultaneously writing new data and reading data from previously processed data wi thin the same spi transfer. this access procedure is used to reduce the turnaround time for ecb mode, see 9.1.5. in addition, th e security module contains anothe r 128-bit register to store the initial key used for security operations. this initial key is not modified by the security module. 9.1.2 security module preparation the use of the security module requires a configuration of the security engine before starting a security operation. t he required steps are listed in table 9-1. table 9-1. aes engine configuration steps step description description chapter 1 key setup write encryption or decryption key to sram 9.1.3 2 aes mode select aes mode: ecb or cbc select encryption or decryption 9.1.4.1 9.1.4.2 3 write data write plaintext or cipher text to sram 9.1.5 4 start operation start aes operation 5 read data read cipher text or plaintext from sram 9.1.5 before starting any security operation a key mu st be written to the security engine, refer to 9.1.3. the key set up requi res the configur ation of the aes engine key mode using regis ter bits aes_mode (s ram address 0x83, aes_ctrl). the following step selects the aes mode, either electronic code book (ecb) or cipher block chaining (cbc). these modes are explained in more detail in section 9.1.4. further, encryption or decr yption must be selected with register bit aes_dir (sram address 0x83, aes_ctrl). as next the 128-bit plain text or cipher text data has to be provided to the aes hardware engine. the data uses the sram address range 0x84 ? 0x93.
132 8168b-mcu wireless-02/09 AT86RF212 an encryption or decryption is initiate d with register bit aes_request = 1 (sram address 0x83, aes_ctrl or the mirrored version with sram address 0x94, aes_ctrl_mirror). the aes module control registers are only accessible using sram read and write accesses on address space 0x82 to 0x94. configuring the aes mode, providing the data and starting a decryption or encryption operation can be combined in a single sram access. notes ? no additional register access is required to operate the security block. ? using aes in trx_off state requires an activated clock at pin 17 (clkm), i.e. register bits clkm_ctrl 0. for further details refer to section 7.7.4. ? access to the security block is not possi ble while the radio transceiver is in state sleep. ? all configurations of the security module, the sram content and keys are reset during sleep or reset states. ? a read or write access to register 0x83 (aes_ctrl) during aes operation terminates the current processing. 9.1.3 security key setup the setup of the key is prepared by se tting register bits aes_mode = 0x1 (sram address 0x83, aes_ctrl). afterwards the 128 bit key must be written to sram addresses 0x84 thr ough 0x93 (registers aes_key). it is recommended to combine the setting of control register 0x83 (aes_ctrl) a nd the 128 bit key transfer using only one sram access starting from address 0x83. the address space of the 128-bit key and 12 8-bit data is identical from programming point of view. however, both use different pages which are selected by register bit aes_mode before storing the data. a read access to registers aes_key (0x84 ? 0x93) returns the last round key of the preceding security operation. after an ecb encr yption operation, this is the key that is required for the corresponding ecb decryption operation. however, the initial aes key, written to the security module in advance of an aes run, see step 1 in table 9-1, is not modified duri ng an aes operation. this initial key is used for the next aes run even it cannot be read from aes_key. note ? ecb decryption is not requ ired for ieee 802.15.4 or zigbee security processing. the AT86RF212 provides this functionality as an additional feature. 9.1.4 security operation modes 9.1.4.1 electro nic code book (ecb) ecb is the basic operating mode of the se curity module. after setting up the initial aes key, register bits aes_mode = 0 (s ram address 0x83, aes_ctrl) sets up ecb mode. register bit aes_dir (sram address 0x83, aes_ctrl) selects the direction, either encryption or decryption. the data to be processed has to be written to sram addresses 0x84 through 0x 93 (registers aes_state). an example for a programming sequence is shown in figure 9-1. this example assume s that a suitable key has been loaded before.
133 8168b-mcu wireless-02/09 AT86RF212 a security operation can be started within one sram access by appending the start command aes_request = 1 (register 0x 94, aes_ctrl_mirror) to the spi sequence. register aes_ctrl _mirror is a mirrored vers ion of register 0x83 (aes_ctrl). figure 9-1. ecb programming spi sequence ? encryption 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 byte 1 (address) byte 0 (cmd.) byte 18 ?. 1 0 0 0 0 0 0 0 data_15[7:0] byte 19 (aes cmd) byte 2 (aes cmd) data_0[7:0] byte 3 ecb, encryption 0x83 sram write aes start summarizing, the following steps are required to perform a security operation using only one spi access: 1. configure spi access a) sram write, refer to section 4.3 b) start add ress 0x83 2. configure aes operation address 0x 83: select ecb mode, direction 3. write 128-bit data block addresses 0x84 ? 0x93: either plain or cipher text 4. start aes operation address 0x94 : start aes operation, ecb mode this sequence is recommended because t he security operation is configured and started within one spi transaction. the ecb encryption operat ion is illustrated in figure 9-2. figure 9-3 shows the ecb decryption m ode, which is supported in a similar way. figure 9-2. ecb mode - encryption block cipher encryption encryption key plaintext ciphertext block cipher encryption encryption key plaintext ciphertext
134 8168b-mcu wireless-02/09 AT86RF212 figure 9-3. ecb mode - decryption block cipher decryption decryption key plaintext ciphertext block cipher decryption decryption key plaintext ciphertext when decrypting, due to the nature of aes al gorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. this last round key is the content of the key addr ess space stored after running one full encryption cycle, and must be saved for decryption. if the decryption key has not been saved, it has to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching the resulting round key from the key memory, and writing it back into the key memory as the decryption key. ecb decryption is not used by either ieee 802.15.4 or zigbee frame security. both of these standards do not directly encrypt t he payload, but rather a nonce instead, and protect the payload by applying an xor operation between the resulting (aes-) cipher text and the original payload. as the nonce is the same for encryption and decryption only ecb encryption is required. decrypti on is performed by xoring the received cipher text with its own encryption result respectively, which results in the original plaintext payload upon success. 9.1.4.2 cipher block chaining (cbc) in cbc mode, the result of a previous aes operation is xored with the new incoming vector, forming the new plaintext to encrypt, see figure 9-4. this mode is used for the comp utation of a cryptographic chec ksum (message integrity code, mic). figure 9-4. cbc mode - encryption block cipher encryption encryption key ciphertext block cipher encryption plaintext ciphertext plaintext initialization vector (iv) encryption key ecb mode cbc mode
135 8168b-mcu wireless-02/09 AT86RF212 after preparing the aes key and defining the aes operation direction using sram register bit aes_dir, the data has to be provided to the aes engine and the cbc operation can be started. the first cbc run has to be configured as ecb to process the initial data (plaintext xored with an initialization vector provi ded by the microcontrol ler). all succeeding aes runs are to be configured as cbc by setti ng register bits aes_mode = 0x2 (register 0x83, aes_ctrl). register bit aes_dir (regi ster 0x83, aes_ctrl) must be set to aes_dir = 0 to enable aes encryption. the data to be processed has to be transferred to the sram starting with addr ess 0x84 to 0x93 (register aes_state). setting register bit aes_request = 1 (register 0x94, aes_ctrl_mirror) as described in section 9.1.4 starts the first encryption within one sram access. this cau ses the next 128 bits of plaintext data to be xored with the previous cipher text data, see figure 9-4. accordi ng to ieee 802.15.4 t he input for the very first cbc operation has to be prepared by a xoring a plaintext with an in itialization vector (iv). the value of the initialization vector is 0. however, for non- compliant usage any other initialization vector can be used. this operation has to be prepared by the microcontroller. note that ieee 802.15.4-2006 st andard mic algorithm requi res cbc mode encryption only, as it implements a one-way hash function. 9.1.5 data transfer ? fast sram access the ecb and cbc modules including the aes core are clocked with 16 mhz. one aes operation takes 24 s to execute, refer to parameter 10.4.15 in section 10.4. this mean s that the processing of the data is us ually faster than the transfer of the data via the spi interface. to reduce the overall processing time, the AT86RF212 provides a fast sram access for the address space 0x83 to 0x94. figure 9-5. packet structure ? fast sram access mode sram write mosi phy_status miso byte 0 (cmd) address 0x83 xx xx byte 1 (addr.) byte 2 (cmd) p0[7:0] xx byte 3 byte 4 byte 18 (1) byte 19 0x83 0x85 0x84 0x93 0x94 address mosi miso aes access #0 address p0 p15 ... cmd add cfg start xx xx ... stat xx xx xx 0x83 0x94 ... aes access #1 p0 p15 ... cmd add cfg start xx c14 ... stat xx xx c15 0x83 0x94 ... aes access #n+1 xx xx ... cmd add cfg start xx c14 ... stat xx xx c15 0x83 0x94 ... p1 p14 xx xx p1 p14 c0 c13 xx xx c0 c13 ... ... c0[0:7] p1[7:0] c14[0:7] c15[0:7] p15[7:0] aes run #0 aes run #n ... note: 1. byte 19 is the mirrored version of register aes_ctrl on sram address 0x94, see register description aes_ctrl_mirror for details. the fast sram access allows writing and reading of data simultaneously during one spi access for consecutive aes operations ( aes run ).
136 8168b-mcu wireless-02/09 AT86RF212 for each byte p0 transferred to pin 22 (mosi) , the previous content of the respective aes register c0 is clocked out at pin 20 (miso) with an offset of one byte. see figure 9-5 a s an example for ? aes access #1 ?. in the example shown in figure 9-5 the initial plaintext p0 ? p15 is written to the sram within ? aes access #0 ?. the last command on addre ss 0x94 (aes_ctrl_mirror) starts the aes operation (? aes run #0 ?). in the next ? aes access #1 ? new plaintext data p0 ? p15 is written to the sram for the second aes run, in parallel the cipher text c0 ? c15 from the first aes run is clocked out at pi n miso. to read the cipher text from the last ? aes run #(n) ?, one dummy ? aes access #(n+1) ? is needed. note that the sram write access always ov erwrites the previous processing result. the fast sram access automatically applie s to all write operations to sram addresses 0x83 to 0x94. 9.1.6 security operation status the status of the security processing is indicated by regist er 0x82 (aes_status). after 24 s aes processing time register bit aes_done changes to 1 (register 0x82, aes_status) indicating that the security operation has finished, see parameter 10.4.15 in section 10.4. 9.1.7 sram register summary the following registers are required to control the security module: table 9-2. sram security module address space overview sram-addr. register name description 0x80 ? 0x81 reserved 0x82 aes_status aes status 0x83 aes_ctrl security module control, aes mode 0x84 ? 0x93 aes_key aes_state depends on aes_mode setting: aes_mode = 1: - contains aes_key (key) aes_mode = 0 | 2: - contains aes_state ( 128 bit data block) 0x94 aes_ctrl_mirror mirror of register 0x83 (aes_ctrl) 0x95 ? 0xff reserved these registers are only accessible using sram write and read, for details refer to section 4.3.3. note that the sram register are reset when entering t he sleep state. 9.1.8 aes sram configuration register r egister 0x82 (aes_status) : this read-only register signals the stat us of the security module and operation. table 9-3. register 0x82 (aes_status) bit 7 6 5 4 name aes_er reserved reserved reserved read/write r r r r reset value 0 0 0 0
137 8168b-mcu wireless-02/09 AT86RF212 bit 3 2 1 0 name reserved reserved reserved aes_done read/write r r r r reset value 0 0 0 0 ? bit 7 ? aes_er this sram register bit indicates an error of the aes module. an error may occur for instance after an access to sram regi ster 0x83 (aes_ctrl) while an aes operation is running or after or after reading less than 128 bits from sram register space 0x84 - 0x93 (aes_state). table 9-4. aes core operation status register bit value description 0 no error of the aes module aes_er 1 aes module error ? bit 6:1 ?reserved ? bit 0 ? aes_done table 9-5. aes core operation status register bit value description 0 aes operation has not been completed aes_done 1 aes operation has been completed register 0x83 (aes_ctrl) : this register controls the operation of t he security module. a read or write access during aes operation terminates the current processing. table 9-6. register 0x83 (aes_ctrl) bit 7 6 5 4 name aes_request aes_mode[2] aes_mode[1] aes_mode[0] read/write w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name aes_dir reserved reserved reserved read/write r/w r r r reset value 0 0 0 0 ? bit 7 ? aes_request a write access with aes_request = 1 initiates the aes operation. ? bit 6:4 ? aes_mode this register bit sets the aes operation mode.
138 8168b-mcu wireless-02/09 AT86RF212 table 9-7. aes mode register bits value description 0 ecb mode, refer to 9.1.4.1 1 key mode, refer to 9.1.3 2 cbc mode, refer to 9.1.4.2 aes_mode 3 ? 7 reserved ? bits 3 ? aes_dir this register bit sets the aes operation dire ction, either encryption or decryption. table 9-8. aes direction register bit value description 0 aes encryption (ecb, cbc) aes_dir 1 aes decryption (ecb) ? bit 1:0 ? reserved register 0x84 (aes_ctrl_mirror): register 0x84 is a mirrored version of register 0x83 (aes_ctrl), for details refer to register 0x83 (aes_ctrl). table 9-9. register 0x84 (aes_ctrl_mirror) bit 7 6 5 4 name aes_request aes_mode[2] aes_mode[1] aes_mode[0] read/write w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name aes_dir reserved reserved reserved read/write r/w r r r reset value 0 0 0 0 this register could be used to start a securi ty operation within a single sram access by appending it to the data stream and se tting register bit aes_request = 1. 9.2 random number generator 9.2.1 overview the AT86RF212 provides a 2-bit random number generator. this random number can be used to: ? generate random seeds for csma-ca algorithm see section 5.2 ? generate random values fo r aes key generation see section 9.1 the ra ndom number is updated every 1 s in basic operating mode receive states. the values are stored in register bits rnd_value (register 0x06, phy_rssi).
139 8168b-mcu wireless-02/09 AT86RF212 9.2.2 register description r egister 0x06 (phy_rssi) : register 0x06 (phy_rssi) is a multi purpose register to indicate fcs validity, to provide random numbers and an rssi value. table 9-10. register 0x06 (phy_rssi) bit 7 6 5 4 name rx_crc_valid rnd_value[1] rnd_value[0] rssi read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name rssi rssi rssi rssi read/write r r r r reset value 0 0 0 0 ? bit 7 ? rx_crc_valid refer to register description in section 6.3.5. ? bit 6:5 ? rnd_value the 2-bit random value can be retrieved by reading register bits rnd_value. note that the radio transceiver shall be in basic operating mode receive state. the values are updated each 1 s. ? bit 4:0 ? rssi refer to register description in section 6.4.4. 9.3 differential output supporting softwa re c ontrolled antenna diversity digital output pins dig1 and dig2 can be used to drive a general purpose differential signal. the following sections describe software controlled antenna diversity as one possible application. 9.3.1 overview due to multipath propagation effects betwe en network nodes, the receive signal strength may vary and affects the link quality, even for small changes of the antenna location. these fading effects can result in an increased error floor or loss of the connection between devices. to improve the reliability of an rf connection between network nodes, antenna diversity can be applied to reduce effects of multipath propagation and fading. antenna diversity uses two antennas to select the most reliable rf signal path. to ensure highly independent receive signals on both antenna s, the antennas should be carefully separated from each other. the AT86RF212 supports software controlled antenna diversity, i.e. the microcontroller controls which antenna is used for transmissio n and reception. this is done by register settings. antenna diversity can be used in basic and extended operating modes and can also be combined with other features and operating modes like high data rate modes and rx/tx indication.
140 8168b-mcu wireless-02/09 AT86RF212 9.3.2 application example a block diagram for a typical application is shown in figure 9-6. the u se of pins 9 and 10 (dig 1 and dig2) for antenna diversity is enabled by ant_ext_sw_en = 1 (register 0x0d, ant_div). in this case, the internal connection of the control pins 9 and 10 to digital ground is disabled (refer to section 2.2.2), and they provide a differential control si gnal to the antenna switch (sw1). for transmission and reception, the ant enna defined by register bits ant_ctrl (register 0x0d, ant_div) is selected. figure 9-6. antenna diversity ? block diagram 6 5 4 3 2 1 910 AT86RF212 dig3 dig4 avss rfp rfn avss dig1 dig2 balun ant0 ant1 rf- switch b1 sw1 ... 9.3.3 register description r egister 0x0d (ant_div) : the ant_div register controls antenna diversity. table 9-11. register 0x0d (ant_div) bit 7 6 5 4 name reserved reserved reserved reserved read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 name reserved ant_ext_sw_en ant_ctrl[1] ant_ctrl[0] read/write r r/w r/w r/w reset value 0 0 0 1 ? bit 7:3 ? reserved ? bit 2 ? ant_ext_sw_en if enabled, pin 9 (dig1) and pin 10 (dig2) become output pins and provide a differential control signal for an antenna diversity switch . the selection of a specific antenna is done according to register bits ant_ctrl.
141 8168b-mcu wireless-02/09 AT86RF212 if rx frame time stamping (refer to section 9.5) is used in combination with antenna div ersity, dig1 is used for antenna diversity and dig2 is used for rx frame time stamping. AT86RF212 do not provide a differe ntial control signal in this case, see figure 3-2. if the register bit is set, the control pins di g1/dig2 are activated in all radio transceiver states as long as register bit ant_ext_ sw_en is set. if the AT86RF212 is not in a receive or transmit state, it is recommended to disable register bit ant_ext_sw_en to reduce the power consumption or avoid le akage current of an external rf switch, especially during sleep state. if register bit ant_ext_sw_en = 0, output pins dig1 and dig2 are internally connected to digital ground. table 9-12. antenna diversity rf switch enable register bit value description 0 antenna diversity rf switch control disabled ant_ext_sw_en 1 antenna diversity rf switch control enabled ? bit 1:0 ? ant_ctrl these register bits provide a static control of an antenna diversity switch. table 9-14. antenna diversity switch control register bit value description 0 reserved 1 antenna 0 dig1 = l dig2 = h 2 antenna 1 dig1 = h dig2 = l ant_ctrl 3 reserved 9.4 rx/tx indicator the main features are: ? rx/tx indicator to control an external rf front-end ? microcontroller independent rf front-end control ? providing tx timing information 9.4.1 overview while ieee 802.15.4 is targeting low cost and low power applications, solutions supporting higher transmit output power are occasionally desirable. to simplify the control of an optional external rf front-end, a differential control pin pair can indicate that the AT86RF212 is currently in transmit mode. the control of an external rf front-end is done via digital control pins dig3/dig4. the function of this pin pair is enabled with register bit pa_ext_en (register 0x04, trx_ctrl_1). while the transmi tter is turned off, pin 1 (dig3) is set to low level and pin 2 (dig4) to high level. if the radio transc eiver starts to transmit, the two pins change the polarity. this differential pin pair can be used to control pa, lna, and rf switches. if the AT86RF212 is not in a receive or trans mit state, it is recommended to disable register bit pa_ext_en (register 0x04, trx_ctrl_1) to reduce the power
142 8168b-mcu wireless-02/09 AT86RF212 consumption or avoid leakage current of external rf switches and other building blocks, especially during sleep state. if register bits pa_ext_en = 0, output pins dig3/dig4 are internally connected to analog ground. 9.4.2 external rf-front end control when using an external rf front-end including a power amplifier (pa), it may be required to adjust the setup time of the external pa relative to the internal building blocks to optimize the overall power spectral density (psd) mask. figure 9-8. tx power ramping control of rf front-end for 250 kbit/s o-qpsk mode 0 6810 trx_state slp_tr pll_on 2 12 14 16 18 length [s] 4 pa pa_lt dig3 dig4 modulation busy_tx tx data the start-up sequence of the individual building blocks of the internal transmitter is shown in figure 9-8, where transmission is act uall y initiated by the rising edge of pin 11 (slp_tr). the radio transceiver state changes from pll_on to busy_tx and the pll settles to the transmit frequency within 1 symbol period. the modulation starts 1 symbol period after the rising edge of slp_tr. during this time, the internal pa is initialized. the control of the external pa is done via the differential pin pair dig3/dig4. dig3 = h / dig4 = l indicates that the transmission starts and can be used to enable the external pa. the timing of pins dig3/dig4 can be adjusted relative to the start of the frame using register bits pa_lt (register 0x16, rf_ctrl_0). for details refer to section 7.3.5. 9.4.3 register description regis ter 0x04 (trx_ctrl_1) : the trx_ctrl_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. table 9-15. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0
143 8168b-mcu wireless-02/09 AT86RF212 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode irq_mask_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en this register bit enables pin 1 (dig3) and pin 2 (dig4) to indicate the transmit state of the radio transceiver. table 9-16. rf front-end control pins pa_ext_en state pin value description dig3 l 0 n/a dig4 l external rf front-end control disabled dig3 h busy_tx dig4 l dig3 l 1 (1) other dig4 h external rf front-end control enabled note: 1. it is recommended to set pa_ext_en = 1 only in receive or transmit states to reduce the power consumption or avoid leak age current of external rf switches or other building blocks, especi ally during sleep state. ? bit 6 ? irq_2_ext_en refer to section 9.5. ? bit 5 ? tx_auto_crc_on refer to section 6.3. ? bit 4 ? rx_bl_ctrl refer to section 9.6. ? bit 3:2 ? spi_cmd_mode refer to section 4.4.1. ? bit 1 ? irq_mask_mode refer to section 4.7. ? bit 0 ? irq_polarity refer to section 4.7. 9.5 rx frame time stamping 9.5.1 overview to determine the exact timing of an incoming frame, e.g. for beaconing networks, the reception of this frame can be signaled to the microcontroller via pin 10 (dig2). the pin turns from l to h after detection of a valid phr. when enabled, dig2 is set to dig2 = h at the same time as irq_2 (rx_start), even if irq_2 is disabled. the pin remains high for the length of the fr ame receive procedure, see figure 9-9. this fu nction is enabled with register bit irq_2_ext_en (register 0x04, trx_ctrl_1). pin 10 (dig2) can be connected to a timer capture unit of the microcontroller.
144 8168b-mcu wireless-02/09 AT86RF212 if this pin is not used for rx frame time stamping, it can be configured for antenna diversity, refer to section 9.3. otherwise, this pin is in t ernally connected to ground. figure 9-9. timing of rx_start and dig2 for rx frame time stamping within 250 kbit/s o-qpsk mode 128 160 192 0 192 + m * 32 time [s] rx frame on air irq_2 (rx_start) t irq rx_on rx_on irq trx_state interrupt latency preamble sfd phr psdu (250 kb/s) 41 1 m < 128 number of octets frame content trx_end t irq busy_rx dig2 (rx frame time stamp) note: timing figures refer to section 10.4. 9.5.2 register description regis ter 0x04 (trx_ctrl_1) : register 0x04 (trx_ctrl_1) is a multi purpo se register to control various operating modes and settings of the radio transceiver. table 9-17. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode irq_mask_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en refer to section 9.4. ? bit 6 ? irq_2_ext_en if this register bit is set, the rx frame time stamping mode is enabled. an incoming frame with a valid phr is signaled via pin 10 (dig2). the pin remains at high level until the end of the frame receive procedure, see figure 9-9. ? bit 5 ? tx_auto_crc_on refer to section 6.3. ? bit 4 ? rx_bl_ctrl refer to section 9.6. ? bit 3:2 ? spi_cmd_mode refer to section 4.4.1.
145 8168b-mcu wireless-02/09 AT86RF212 ? bit 1 ? irq_mask_mode refer to section 4.7. ? bit 0 ? irq_polarity refer to section 4.7. 9.6 frame buffer empty indicator 9.6.1 overview for time critical applications, it may be desirable to read the frame data as early as possible. to accomplish this, the frame bu ffer empty status can be indicated to the microcontroller through a dedicated pin. pin 24 (irq) can be configured as frame buffer empty indicator during the frame buffer read access. this mode is enabled by register bit rx_bl_ctrl (register 0x04, trx_ctrl_1). as shown in figure 9-10, the pin 24 turns from ir q i nto frame buffer empty indicator after the frame buffer read access command has been transferred on the spi bus, see (1) in figure 9-10. the pin 24 turns back to its regular function irq when the frame buffer read p rocedure has been completed by /sel = h, see (4) . figure 9-10. timing diagram of frame buffer empty indicator /sel mosi miso irq sclk command phy_status xx irq_status command phy_status xx phr[7:0] xx psdu[7:0] irq_2 (rx_start) xx psdu[7:0] xx psdu[7:0] t 13 xx lqi[7:0] command pyh_status xx irq_status irq_3 (trx_end) frame buffer empty indicator (1) (4) (3) notes (2) the microcontroller has to observe pin 24 during the frame buffer read procedure. a frame buffer read access can proceed as long as pin 24 = l, see (2) . pin 24 = h indicates that the frame buffer is current ly not ready for another spi cycle, see (3) , and thus the frame buffer read procedure has to wait for valid data accordingly. the frame buffer empty indicator pin 24 (irq) becomes effective t 13 = 750 ns after the rising edge of last sclk clock of the frame buffer read command byte. after finishing the frame buffer read access by releasing /sel = h, see (4) , pending interrupts are immediately indicated by pin irq. if during the frame buffer read access a receive error occurs (e.g. a pll unlock), the frame buffer empty indicator locks on 'empty' (pin 24 = h) too. to prevent possible deadlocks, the microcontroller should impose a timeout counter that checks whether the frame buffer empty indicator remains logic high for more than 2 octet periods. a new byte must have been arrived at the frame buffer during that period. if not, the frame buffer read access should be aborted.
146 8168b-mcu wireless-02/09 AT86RF212 9.6.2 register description regis ter 0x04 (trx_ctrl_1) : the trx_ctrl_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. table 9-18. register 0x04 (trx_ctrl_1) bit 7 6 5 4 name pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name spi_cmd_mode spi_cmd_mode irq_mask_mode irq_polarity read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? pa_ext_en refer to section 9.4. ? bit 6 ? irq_2_ext_en refer to section 9.5. ? bit 5 ? tx_auto_crc_on refer to section 6.3. ? bit 4 ? rx_bl_ctrl if this register bit is set, the frame buffer empty indicator is enabled. after sending a frame buffer read command, refer to section 4.3, pin 24 (irq) indicates that an access to the f rame buffer is not possible since psdu data are not available yet. pin 24 (irq) does not indicate any interrupt during this time. table 9-19. frame buffer empty indicator register bit value description 0 frame buffer empty indicator disabled rx_bl_ctrl 1 frame buffer empty indicator enabled ? bit 3:2 ? spi_cmd_mode refer to section 4.4.1. ? bit 1 ? irq_mask_mode refer to section 4.7. ? bit 0 ? irq_polarity refer to section 4.7. 9.7 dynamic frame buffer protection 9.7.1 overview the AT86RF212 continues the reception of in coming frames as long as it is in any receive state. when a frame is successfully received and stored in the frame buffer, the following frame overwrites the frame buffer content again.
147 8168b-mcu wireless-02/09 AT86RF212 to relax the timing requirements of a frame buffer read access, dynamic frame buffer protection prevents that a new incoming fram e overwrites the frame buffer as long as the frame buffer read access has not been completed by /sel = h, refer to section 4.3. a receive d frame is automatically protected against overwriting: ? in basic operating mode, if its fcs is valid ? in extended operating mode, if an irq_3 (trx_end) is generated the dynamic frame buffer protection is enabled, if register bit rx_safe_mode (register 0x0c, trx_ctrl_2) is set and the transceiver state is rx_on or rx_aack_on. note that dynamic frame buffer protection only prevents write accesses from the air interface ? not from the spi interface. a fr ame buffer or sram write access may still modify the frame buffer content. 9.7.2 register description regis ter 0x0c (trx_ctrl_2) : the trx_ctrl_2 register is a multi purpose register to control various settings of the radio transceiver. table 9-20. register 0x0c (trx_ctrl_2) bit 7 6 5 4 name rx_safe_mode trx_off_avdd_en oqpsk_scram_en oqpsk_sub1_rc_en read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 name bpsk_oqpsk sub_mode oqpsk_data_rate oqpsk_data_rate read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 ? rx_safe_mode if this bit is set, dynamic fram e buffer protection is enabled. table 9-21. dynamic frame buffer protection mode register bit value description 0 disable dynamic frame buffer protection rx_safe_mode (1) 1 enable dynamic frame buffer protection note: 1. dynamic frame buffer protection is deactivated automatically with the rising edge of pin 23 (/sel) of a frame buffer read access, see section 4.3.2, or radio t ransceiver state change from rx_on or rx_aack_on to another state. ? bit 6 ? trx_off_avdd_en refer to section 5.1.4.3. ? bit 5 ? oqpsk_scram_en refer to section 7.1.5.
148 8168b-mcu wireless-02/09 AT86RF212 ? bit 4 ? oqpsk_sub1_rc_en refer to section 7.1.5. ? bit 3 ? bpsk_oqpsk refer to section 7.1.5. ? bit 2 ? sub_mode refer to section 7.1.5. ? bit 1:0 ? oqpsk_data_rate refer to section 7.1.5. 9.8 configurable start-of-frame delimiter (sfd) 9.8.1 overview the sfd is a field indicating the end of the shr and the start of the packet data. the length of the sfd is 1 octet (8 symbol s for bpsk and 2 symbols for o-qpsk). this octet is used for byte synchronization only and is not included in the frame buffer. the value of the sfd could be changed if it is need ed to operate non ieee 802.15.4 compliant networks. an ieee 802.15.4 compli ant network node does not synchronize to frames with a different sfd value. due to the way the shr is formed, it is not recommended to set the low-order 4 bits to 0. 9.8.2 register description r egister 0x0b (sfd_value) : this register contains the one octet start-of -frame delimiter (sfd) to synchronize to a received frame. table 9-22. register 0x0b (sfd_value) bit 7 6 5 4 3 2 1 0 name sfd_value[7:0] read/write r/w reset value 1 0 1 0 0 1 1 1 ? bit 7:0 ? sfd_value for compliant ieee 802.15.4 networks set sfd_value = 0xa7, as specified by [1]. this is the default value of the register. to establish non ieee 802.15.4 compliant networks, the sfd value can be changed to any other value. if enabled, irq_2 (rx_start) is issued only if the received sfd matches sfd_value and a valid phr is received.
149 8168b-mcu wireless-02/09 AT86RF212 10 electrical characteristics 10.1 absolute maximum ratings note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. no. symbol parameter condition min. typ. max. units 10.1.1 t stor storage temperature -50 150 c 10.1.2 t lead lead temperature t = 10s soldering profile compliant with ipc/jedec j-std-020b 260 c 10.1.3 v esd esd robustness human body model (hbm), compliant to [5] charged device model, compliant to [6] 4 750 kv v 10.1.4 p rf input rf level 10 dbm 10.1.5 v dig voltage on all pins except pins 4, 5, 13, 14, 29 -0.3 v dd +0.3 4.0 v 10.1.6 v ana voltage on pins 4, 5, 13, 14, 29 -0.3 2 v 10.2 operating range no. symbol parameter condition min. typ. max. units 10.2.1 t op operating temperature range -40 85 c 10.2.2 v dd supply voltage voltage on pins 15, 28 (1) 1.8 3.0 3.6 v 10.2.3 v dd1.8 supply voltage voltage on pins 13, 14, 29 external voltage supply (1)(2) 1.7 1.8 1.9 v note: 1. even if an implementation uses the external 1.8 v voltage supply v dd1.8 , it is required to connect v dd . 2. register 0x10 (vreg_ctrl) needs to be programmed to disable internal voltage regulators and supply bl ocks, refer to section 7.5. 10.3 digital pin specifications test condition: t op = 25c no. symbol parameter condition min. typ. max. units 10.3.1 v ih high level input voltage (1) v dd -0.4 v 10.3.2 v il low level input voltage (1) 0.4 v 10.3.3 v oh high level output voltage (1) for all output driver strength defined in trx_ctrl_0 v dd -0.4 v 10.3.4 v ol low level output voltage (1) for all output driver strength defined in trx_ctrl_0 0.4 v
150 8168b-mcu wireless-02/09 AT86RF212 note: 1. the capacitive load should not be larger than 50 pf for all i/os when using the default driver strength settings, refer to section 2.2.2.1. generally, large load capac itances increase the overall current consumption. 10.4 digital interface timi ng characteristics test conditions: t op = 25c, v dd = 3.0 v, c l = 50 pf no. symbol parameter condition min. typ. max. units 10.4.1 f sync sclk frequency synchronous operation 8 mhz 10.4.2 f async sclk frequency asynchronous operation 7.5 mhz 10.4.3 t 1 /sel falling edge to miso active 180 (7) ns 10.4.4 t 2 sclk falling edge to miso out data hold time 25 (7) ns 10.4.5 t 3 mosi setup time 10 (7) ns 10.4.6 t 4 mosi hold time 10 (7) ns 10.4.7 t 5 lsb last byte to msb next byte 250 (8)(10) ns 10.4.8 t 6 /sel rising edge to miso tri state 10 (8) ns 10.4.9 t 7 slp_tr pulse width tx start trigger 62.5 note (1) ns 10.4.10 t 8 spi idle time: sel rising to falling edge spi read/write, standard sram and frame access modes; idle time between consecutive spi accesses 250 (8) ns 10.4.11 t 8 spi idle time: sel rising to falling edge fast sram read/write access mode, refer to section 9.1.5; idle t ime between consecutive spi accesses 500 (8) ns 10.4.12 t 9 sclk rising edge lsb to /sel rising edge 250 (8) ns 10.4.13 t 10 reset pulse width 10 clock cycles at 16 mhz 625 ns 10.4.14 t 11 spi access latency after reset 10 clock cycles at 16 mhz 625 ns 10.4.15 t 12 aes core cycle time 24 s 10.4.16 t 13 dynamic frame buffer protection: irq latency 750 ns 10.4.17 f clkm clock frequency at pin 17 (clkm) programmable via register 0x03 (trx_ctrl_0) 0 (2) 1 (2) 2 (2) 4 (2) 8 (2) 16 (2) 1/4 (2) 1/50 (3) 1/25 (4) 1/40 (5) 1/16 (6) mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz 10.4.18 t irq irq_2, irq_3, irq_4 latency relative to the event to be indicated 9 (9) s
151 8168b-mcu wireless-02/09 AT86RF212 notes: 1. maximum pulse width less than (tx frame length + 16 s) 2. all modes 3. only in bpsk mode with f psdu = 20 kbit/s 4. only in bpsk mode with f psdu = 40 kbit/s 5. only in o-qpsk mode with f psdu = 100/200/400 kbit/s 6. only in o-qpsk mode with f psdu = 250/500/1000 kbit/s 7. see figure 4-3 8. see figure 4-2 9. see figure 5-2 10. for fast sram read/write accesses on address space 0x82 ? 0x94 the time t 5 (min.) increases to 450 ns. 10.5 general transceiver specifications test conditions: t op = 25c, v dd = 3.0 v no. symbol parameter condition min. typ. max. units 10.5.1 f rf frequency range 1.0 mhz spacing 0.1 mhz spacing 0.1 mhz spacing 0.1 mhz spacing 769 769 857 903 935 794.5 882.5 928.5 mhz mhz mhz mhz 10.5.2 f chip chip rate bpsk as specified in [1] bpsk as specified in [1] o-qpsk as specified in [1] o-qpsk as specified in [1] 300 600 400 1000 kchip/s kchip/s kchip/s kchip/s 10.5.3 f hdr header bit rate (shr, phr) bpsk as specified in [1] bpsk as specified in [1] o-qpsk as specified in [1] o-qpsk as specified in [1] 20 40 100 250 kbit/s kbit/s kbit/s kbit/s 10.5.4 f psdu psdu bit rate bpsk as specified in [1] bpsk as specified in [1] o-qpsk as specified in [1] o-qpsk as specified in [1] o-qpsk o-qpsk o-qpsk o-qpsk 20 40 100 250 200 400 500 1000 kbit/s kbit/s kbit/s kbit/s kbit/s kbit/s kbit/s kbit/s 10.5.5 f clk crystal oscillator frequency reference oscillator 16 mhz 10.5.6 t xtal reference oscillator settling time leaving sleep state to clock available at pin 17 (clkm) 0.5 1 ms 10.5.7 reference oscillator accuracy f psdu = 20/40/100/250 kbit/s f psdu = 200/400/500/1000 kbit/s -60 (1) -40 +60 (1) +40 ppm ppm 10.5.8 battery monitor threshold deviation -0.1 0.0 0.1 v note: 1. a reference frequency accuracy of 40 ppm is required by [1]
152 8168b-mcu wireless-02/09 AT86RF212 10.6 transmitter characteristics test conditions: t op = 25c, v dd = 3.0 v no. symbol parameter condition min. typ. max. units 10.6.1 p tx tx output power normal mode boost mode (1) 5 10 dbm dbm 10.6.2 p range output power range 22 steps 21 db 10.6.3 p acc output power tolerance oqpsk-100, 868.3 mhz, p tx = 0 dbm (register 0x05 value = 0x65) 3 db 10.6.4 p 1db 1 db compression point normal mode boost mode 5 8 dbm dbm 10.6.5 evm error vector magnitude o-qpsk in european band according to [1] otherwise 25 6 % rms % rms 10.6.6 p harm harmonics 2nd harmonic 3rd harmonic bpsk modulation, 868.3 mhz common mode signal measured single ended @ rfp into 50 ? p tx = 0 dbm p tx = 5 dbm differential signal measured with balun (see table 3-1) p tx = 0 dbm p tx = 5 dbm -35 -27 -41 -43 dbm dbm dbm dbm 10.6.7 psd power spectrum density mask european band, measured at first side lobe using 100 khz bandwidth (integrated power from 300 to 400 khz offset from carrier), oqpsk-100, 868.3 mhz, p tx = 0 dbm (register 0x05 value = 0x65) -42 dbm 10.6.8 p spur spurious emissions 30 ? 1000 mhz 1 ? 12.75 ghz except harmonics -57 -47 dbm dbm note: 1. increased harmonics and spurious in boost mode
153 8168b-mcu wireless-02/09 AT86RF212 10.7 receiver characteristics test conditions: t op = 25c, v dd = 3.0 v no. symbol parameter condition min. typ. max. units 10.7.1 p sens receiver sensitivity 20 kbit/s (1) 40 kbit/s (1) 100 kbit/s (1) 250 kbit/s (1) 200 kbit/s 400 kbit/s 500 kbit/s 1000 kbit/s awgn channel, per 1% psdu length of 20 octets psdu length of 20 octets psdu length of 20 octets psdu length of 20 octets psdu length of 127 octets psdu length of 127 octets psdu length of 127 octets psdu length of 127 octets -110 -108 -101 -101 -98 -93 -98 -93 dbm dbm dbm dbm dbm dbm dbm dbm 10.7.2 nf noise figure 7 db 10.7.3 p rxmax maximum rx input level per 1%, psdu length of 20 octets -5 dbm 10.7.4 adjacent and alternate adjacent channel rejection bpsk with 20 kbit/s p rx = -89 dbm, per 1% f = -1 mhz f = +1 mhz f = -2 mhz f = +2 mhz 32 19 37 38 db db db db 10.7.5 adjacent and alternate adjacent channel rejection bpsk with 40 kbit/s p rx = -89 dbm, per 1% f = -2 mhz f = +2 mhz f = -4 mhz f = +4 mhz 36 35 52 53 db db db db 10.7.6 adjacent and alternate adjacent channel rejection o-qpsk with 100 kbit/s p rx = -82 dbm, per 1% f = -1 mhz f = +1 mhz f = -2 mhz f = +2 mhz 25 16 34 35 db db db db 10.7.7 adjacent and alternate adjacent channel rejection o-qpsk with 250 kbit/s p rx = -82 dbm, per 1% f = -2 mhz f = +2 mhz f = -4 mhz f = +4 mhz 27 27 49 49 db db db db 10.7.8 lo leakage measured at 2 ? f c - 4 mhz with balun (see table 3-1) -71 dbm 10.7.9 iip3 3 rd -order intercept point 868.3 mhz, maximum gain offset freq. interf. a = 2 mhz offset freq. interf. b = 4 mhz -9 dbm 10.7.10 iip2 2 nd -order intercept point 868.3 mhz, maximum gain offset freq. interf. a = 3.2 mhz offset freq. interf. b = 8.2 mhz 53 dbm 10.7.11 rssi range o- qpsk-250 modulation lower threshold upper threshold -97 -12 dbm dbm
154 8168b-mcu wireless-02/09 AT86RF212 no. symbol parameter condition min. typ. max. units 10.7.12 rssi tolerance 5 db note: 1. ieee 802.15.4-2006 compliant 10.8 current consumption specifications test conditions: t op = 25c, v dd = 3.0 v, clkm = off no. symbol parameter condition min. typ. max. units 10.8.1 i busy_tx supply current transmit state settings for north american band p tx = 0 dbm (normal mode) p tx = 5 dbm (normal mode) p tx = 10 dbm (boost mode) 14 18 24 ma ma ma 10.8.2 i rx_on supply current rx_on (listen) state highest sensitivity (rx_pdt_level = 0) reduced sensitivity (rx_pdt_level > 0) 9.0 8.5 ma ma 10.8.3 i pll_on supply current pll_on state 4.7 ma 10.8.4 i trx_off supply current trx_off state 0.4 ma 10.8.5 i sleep supply current sl eep state 0.2 a 10.9 crystal parameter requirements no. symbol parameter condition min. typ. max. units 10.9.1 f 0 crystal frequency 16 mhz 10.9.2 c l load capacitance 8 14 pf 10.9.3 c 0 crystal shunt capacitance 7 pf 10.9.4 esr series resistance 100 ?
155 8168b-mcu wireless-02/09 AT86RF212 11 register reference the AT86RF212 provides a register space of 64 8-bit registers, used to configure, control, and monitor the radio transceiver. note : all registers not mentioned within the following table are reserved for internal use and must not be overwritten. when writ ing to a register, any reserved bits shall be overwritten only with their reset value. table 11-1. register summary addr. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x00 - - - - - - - - - 0x01 trx_status cca_done cca_status - trx_status[4] trx_status[3] trx_status[2] trx_status[1] trx_status[0] 39, 58, 86 0x02 trx_state trac_status[2] trac_status[1] trac_status[0] trx_cmd[4] trx_cmd[3] trx_cmd[2] trx_cmd[1] trx_cmd[0] 40,59 0x03 trx_ctrl_0 pad_io[1] pad_io[0] pad_io_clkm[1] pad_io_clkm[0] clkm_sha_sel clkm_ctrl[2] clkm_ctrl[1] clkm_ctrl[0] 8,120 0x04 trx_ctrl_1 pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl spi_cmd_mode[1] spi_cmd_mode[0] irq_mask_mode irq_polarity 20, 27, 61, 78,142, 144, 146 0x05 phy_tx_pwr pa_boost gc_pa[1] gc_pa[0] tx_pwr[4] tx_pwr[3] tx_pwr[2] tx_pwr[1] tx_pwr[0] 106 0x06 phy_rssi rx_crc_valid rnd_value[1] rnd_value[0] rssi[4] rssi[3] rssi[2] rssi[1] rssi[0] 78,80, 139 0x07 phy_ed_level ed_level[7] ed_level[6] ed_level[5] ed_level[4] ed_level[3] ed_level[2] ed_level[1] ed_level[0] 83 0x08 phy_cc_cca cca_request cca_mode[1] cca_mode[0] channel[4] channel[3] channel[2] channel[1] channel[0] 86,89, 125 0x09 cca_thres - - - - cca_ed_thres[3] cca_ed_thres[2] cca_ed_thres[1] cca_ed_thres[0] 87,89 0x0a - - - jcm_en - - - - - 0x0b sfd_value sfd_value[7] sfd_value[6] sfd_value[5] sfd_ value[4] sfd_value[3] sfd_value[2] sfd_value[1] sfd_value[0] 148 0x0c trx_ctrl_2 rx_safe_mode trx_off_avdd_en oqpsk_scram_ en oqpsk_sub1_ rc_en bpsk_oqpsk sub_mode oqpsk_data_rate[1] oqpsk_data_rate[0] 95,114, 147 0x0d ant_div - - - - - ant_ext_sw_en ant_ctrl[1] ant_ctrl[0] 140 0x0e irq_mask mask_bat_low mask_trx_ur mask_ami mask_cca_ed_done mask_trx_end mask_rx_start mask_pll_unlock mask_pll_lock 26 0x0f irq_status bat_low trx_ur ami cca_ed_done trx_end rx_start pll_unlock pll_lock 26 0x10 vreg_ctrl avreg_ext avdd_ok - - dvreg_ext dvdd_ok - - 113 0x11 batmon - - batmon_ok batmon_hr batmon_vth[3] batmon_vth[2] batmon_vth[1] batmon_vth[0] 116 0x12 xosc_ctrl xtal_mode[3] xtal_mode[2] xtal_mode[1] xtal_mode[0] xtal_trim[3] xtal_trim[2] xtal_trim[1] xtal_trim[0] 121 0x13 cc_ctrl_0 cc_number[7] cc_number[6] cc_number[5] cc_number[4] cc_number[3] cc_number[2] cc_number[1] cc_number[0] 126 0x14 cc_ctrl_1 - - - - - cc_band[2] cc_ band[1] cc_ band[0] 126 0x15 rx_syn rx_pdt_dis - - - rx_pdt_level[3] rx_pdt_level[2] rx_pdt_level[1] rx_pdt_level[0] 99 0x16 rf_ctrl_0 pa_lt[1] pa_lt[0] - - - - gc_tx_offs[1] gc_tx_offs[0] 105 0x17 xah_ctrl_1 - csma_lbt_mode aack_fltr_res_ft aack_upld_res_ft - aack_ack_time aack_prom_mode - 61, 72, 90 0x18 ftn_ctrl ftn_start - - - - - - - 128 0x19 rf_ctrl_1 rf_mc[3] rf_mc[2] rf_mc[1] rf_mc[0] - - - - 99 0x1a pll_cf pll_cf_start - - pll_cf[4] pll_cf[3] pll_cf[2] pll_cf[1] pll_cf[0] 126 0x1b pll_dcu pll_dcu_start - - - - - - - 127 0x1c part_num part_num[7] part_num[6] part_num[5] part_num[4] part_num[3] part_num[2] part_num[1] part_num[0] 21 0x1d version_num version_num[7] version_num[6] version_num[5] ver sion_num[4] version_num[3] version_num[2] version_num[1] version_ num[0] 21 0x1e man_id_0 man_id_0[7] man_id_0[6] man_id_0[5] man_id_0[4] man_id_0[3] man_id_0[2] man_id_0[1] man_id_0[0] 21 0x1f man_id_1 man_id_1[7] man_id_1[6] man_id_1[5] man_id_1[4] man_id_1[3] man_id_1[2] man_id_1[1] man_id_1[0] 22 0x20 short_addr_0 short_addr_0[7] short_addr_0[6] short_addr_0[5] short_addr_0[4] short_a ddr_0[3] short_addr_0[2] short_addr_0[1] sh ort_addr_0[0] 73 0x21 short_addr_1 short_addr_1[7] short_addr_1[6] short_addr_1[5] short_addr_1[4] short_a ddr_1[3] short_addr_1[2] short_addr_1[1] sh ort_addr_1[0] 73 0x22 pan_id_0 pan_id_0[7] pan_id_0[6] pan_id_0[5] pan_id_0[4] pan_id_0[3] pan_id_0[2] pan_id_0[1] pan_id_0[0] 73
156 8168b-mcu wireless-02/09 AT86RF212 addr. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x23 pan_id_1 pan_id_1[7] pan_id_1[6] pan_id_1[5] pan_id_1[4] pan_id_1[3] pan_id_1[2] pan_id_1[1] pan_id_1[0] 73 0x24 ieee_addr_0 ieee_addr_0[7] ieee_addr_0[6] ieee_addr_0[5] ieee_addr_0[4] ieee_addr_0[3] ieee_addr_0[2] ieee_addr_0[1] ieee_ addr_0[0] 74 0x25 ieee_addr_1 ieee_addr_1[7] ieee_addr_1[6] ieee_addr_1[5] ieee_addr_1[4] ieee_addr_1[3] ieee_addr_1[2] ieee_addr_1[1] ieee_ addr_1[0] 74 0x26 ieee_addr_2 ieee_addr_2[7] ieee_addr_2[6] ieee_addr_2[5] ieee_addr_2[4] ieee_addr_2[3] ieee_addr_2[2] ieee_addr_2[1] ieee_ addr_2[0] 74 0x27 ieee_addr_3 ieee_addr_3[7] ieee_addr_3[6] ieee_addr_3[5] ieee_addr_3[4] ieee_addr_3[3] ieee_addr_3[2] ieee_addr_3[1] ieee_ addr_3[0] 74 0x28 ieee_addr_4 ieee_addr_4[7] ieee_addr_4[6] ieee_addr_4[5] ieee_addr_4[4] ieee_addr_4[3] ieee_addr_4[2] ieee_addr_4[1] ieee_ addr_4[0] 75 0x29 ieee_addr_5 ieee_addr_5[7] ieee_addr_5[6] ieee_addr_5[5] ieee_addr_5[4] ieee_addr_5[3] ieee_addr_5[2] ieee_addr_5[1] ieee_ addr_5[0] 75 0x2a ieee_addr_6 ieee_addr_6[7] ieee_addr_6[6] ieee_addr_6[5] ieee_addr_6[4] ieee_addr_6[3] ieee_addr_6[2] ieee_addr_6[1] ieee_ addr_6[0] 75 0x2b ieee_addr_7 ieee_addr_7[7] ieee_addr_7[6] ieee_addr_7[5] ieee_addr_7[4] ieee_addr_7[3] ieee_addr_7[2] ieee_addr_7[1] ieee_ addr_7[0] 75 0x2c xah_ctrl_0 max_frame_retries[3] max_frame_retries[2] max_frame_retries[1] max_frame_retries[0] max_csma_retries[2] max_csma_retries[1] max_csma_retries[0] slotted_operation 63 0x2d csma_seed_0 csma_seed_0[7] csma_seed_0[6] csma_seed_0[5] csma_seed_0[4] csma_seed_0[3] csma_seed_0[2] csma_seed_0[1] csma_see d_0[0] 63 0x2e csma_seed_1 aack_fvn_mode[1] aack_fvn_mode[0] aack_set_pd aack_dis_ack aack_i_am_coord csma_seed_1[2] csma_seed_1[1] csma_seed_1[0] 64,75 0x2f csma_be max_be[3] max_be[2] max_be[1] max_be[0] min_be[3] min_be[2] min_be[1] min_be[0] 65 ?. - - - - - - - - - the reset values of the AT86RF212 registers in state p_on (1, 2, 3) are shown in table 11-2. note : all reset values in table 11-2 are only valid after a power on reset. after a reset pro cedure (/rst = l) as described in section 5.1.4.5, the reset values of sele cted registers (e.g. regi sters 0x01, 0x10, 0x 11, 0x30) can differ from that in table 11-2. table 11-2. register summary ? reset values address reset value address reset value address reset value address reset value 0x00 0x00 0x10 0x00 (1) 0x20 0xff 0x30 0x00 (3) 0x01 0x00 0x11 0x02 (2) 0x21 0xff 0x31 0x00 0x02 0x00 0x12 0xf0 0x22 0xff 0x32 0x00 0x03 0x19 0x13 0x00 0x23 0xff 0x33 0x00 0x04 0x20 0x14 0x00 0x24 0x00 0x34 0x3f 0x05 0x60 0x15 0x00 0x25 0x00 0x35 0x00 0x06 0x00 0x16 0x31 0x26 0x00 0x36 0x00 0x07 0xff 0x17 0x00 0x27 0x00 0x37 0x00 0x08 0x25 0x18 0x58 0x28 0x00 0x38 0x00 0x09 0x77 0x19 0x00 0x29 0x00 0x39 0x40 0x0a 0x17 0x1a 0x48 0x2a 0x00 0x3a 0x00 0x0b 0xa7 0x1b 0x40 0x2b 0x00 0x3b 0x00 0x0c 0x24 0x1c 0x06 0x2c 0x38 0x3c 0x00 0x0d 0x01 0x1d 0x01 0x2d 0xea 0x3d 0x00 0x0e 0x00 0x1e 0x1f 0x2e 0x42 0x3e 0x00 0x0f 0x00 0x1f 0x00 0x2f 0x53 0x3f 0x00 notes: 1. while the reset value of register 0x10 is 0x00, any practical access to the register is only possible when dvreg is active. so this register is always read out as 0x04. for details refer to section 7.5. 2. while the reset value of register 0x11 is 0x02, any practical access to the register is only possible when batmon is activated. so this register is always read out as 0x22 in p_on state. for details refer to section 7.6.
157 8168b-mcu wireless-02/09 AT86RF212 3. while the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the radio transceiver is accessible. so the register is usually read out as: a) 0x11 after a reset in p_on state b) 0x07 after a reset in any other state
158 8168b-mcu wireless-02/09 AT86RF212 12 abbreviations ack ? acknowledgement adc ? analog-to-digital converter aes ? advanced encryption standard agc ? automatic gain control avreg ? analog voltage regulator awgn ? additive white gaussian noise batmon ? battery monitor bbp ? base-band processor bpf ? band-pass filter bpsk ? binary phase shift keying cbc ? cipher block chaining cca ? clear channel assessment cf ? center frequency crc ? cyclic redundancy check cs ? carrier sense csma-ca ? carrier sense multiple access ? collision avoidance cw ? continuous wave dac ? digital-to-analog converter dvreg ? digital voltage regulator ecb ? electronic code book ed ? energy detect esd ? electro static discharge fcf ? frame control field fcs ? frame check sequence fifo ? first in first out ftn ? filter tuning ic ? integrated circuit if ? intermediate frequency i/o ? input/output irq ? interrupt request ism ? industrial scientific medical lbt ? listen before talk ldo ? low dropout lna ? low-noise amplifier lo ? local oscillator lpf ? low-pass filter lqi ? link quality indication lsb ? least significant bit mac ? medium access control mhr ? mac header mic ? message integrity code miso ? master input slave output mosi ? master output slave input msb ? most significant bit msdu ? mac service data unit o-qpsk ? offset quadrature phase shift keying pa ? power amplifier pan ? personal area network per ? packet error rate phr ? phy header phy ? physical layer pll ? phase-looked loop
159 8168b-mcu wireless-02/09 AT86RF212 ppdu ? phy protocol data unit ppf ? poly-phase filter prbs ? pseudo random binary sequence psd ? power spectrum density psdu ? phy service data unit qfn ? quad flat no-lead package rc ? raised cosine rf ? radio frequency rssi ? received signal strength indicator rx ? receiver sfd ? start-of-frame delimiter shr ? synchronization header spi ? serial peripheral interface sram ? static random access memory srd ? short range device trx ? transceiver tx ? transmitter vco ? voltage controlled oscillator wpan ? wireless personal area network xosc ? crystal oscillator xtal ? crystal
160 8168b-mcu wireless-02/09 AT86RF212 13 ordering information ordering code package voltage range temperature range AT86RF212-zu qn 1.8v ? 3.6v industrial (-40 c to +85 c) lead-free/halogen-free package type description qn 32qn2, 32-lead 5.0x5.0 mm body, 0.50 mm pitch, quad flat no-lead package (qfn) sawn note: t&r quantity 4,000. please contact your local atmel sales office for more detailed ordering information and minimum quantities. 14 soldering information recommended soldering profile is spec ified in ipc/jedec j-std-.020c. 15 package thermal properties thermal resistance velocity [m/s] theta ja [k/w] 0 40.9 1 35.7 2.5 32.0
161 8168b-mcu wireless-02/09 AT86RF212 16 package drawing ? 32qn2
162 8168b-mcu wireless-02/09 AT86RF212 appendix a ? continuous transmission test mode a.1 ? overview the AT86RF212 offers a continuous transmission test mode to support application / production tests as well as certification tests. using this test mode, the radio transceiver transmits continuously a previously transfe rred frame (prbs mode) or a continuous wave signal (cw mode). in cw mode four different signal frequencies per channel can be transmitted: ? f 1 = f ch + 0.25 mhz using o-qpsk 1000 kbit/s mode ? f 2 = f ch - 0.25 mhz using o-qpsk 1000 kbit/s mode ? f 3 = f ch + 0.1 mhz using o-qpsk 400 kbit/s mode ? f 4 = f ch - 0.1 mhz using o-qpsk 400 kbit/s mode f ch is the channel center frequency, refer to section 7.8.2. note, in cw mode it is no t possible to transmit an rf signal directly on the channel center frequency. psdu data in the frame buffer must cont ain at least a valid phr (see section 6.1). it is recomme nded to use a frame of maximum length (127 bytes) and arbitrary psdu data for the prbs mode. after transmission of two symbols, psdu data is repeated continuously. a.2 ? configuration before enabling continuous transmission test mode all register configurations shall be done as follows: ? tx channel setting (optional) ? tx output power setting (optional) ? mode selection (prbs / cw) register write accesses to register 0x36 and 0x1c enable the continuous transmission test mode. the transmission is started by enabling t he pll (trx_cmd = pll_on) and writing the tx_start command to register 0x02. even for cw signal transmission it is requi red to write valid psdu data to the frame buffer. for prbs mode it is recommended to write a frame of maximum length. the detailed programming sequence is shown in table a-1. the column r/w informs about writing (w) or reading (r) a register or the frame buffer. the content of the frame buffer has to be defined for continuous transmission prbs mode or cw mode. to measure the power spectral density (psd) mask of the transmitter it is recommended to use a random sequence of maximum length for the psdu data. to measure cw signals it is necessary to write either 0x00 or 0xff to the frame buffer, for details refer to table a-2.
163 8168b-mcu wireless-02/09 AT86RF212 table a-1. continuous transmission programming sequence step action register r/w value description 1 reset reset AT86RF212 2 register access 0x0e w 0x01 set irq mask register, enable irq_0 (pll_lock) 3 register access 0x04 w 0x00 disable tx_auto_crc_on 4 register access 0x02 w 0x03 set radio transceiver state trx_off 5 register access w set channel, refer to section 7.8.2. 6 register access w set tx output power, refer to section 7.3.4 7 register access 0x01 r 0x08 verify trx_off state 8 register access 0x36 w 0x0f enable continuous transmission test mode ? step # 1 9 register access 0x0c w cw mode: enable high data rate mode without scrambler, 400 kbit/s or 1000 kbit/s (register values 0x0a or 0x0e, respectively) prbs mode: select modulation scheme, refer to section 7.1.5 10 frame buffer write access w write psdu data (even for cw mode), refer to table a-2. frame buffer content varies f or different modulation schemes. 11 register access 0x1c w 0x54 enable continuous transmission test mode ? step # 2 12 register access 0x1c w 0x46 enable continuous transmission test mode ? step # 3 13 register access 0x02 w 0x09 enable pll_on state 14 interrupt event 0x0f r 0x01 wait for irq_0 (pll_lock) 15 register access 0x02 w 0x02 initiate transmission, enter busy_tx state 16 measurement perform measurement 17 register access 0x1c w 0x00 disable continuous transmission test mode 18 reset reset AT86RF212 table a-2. frame buffer content for various continuous transmission modulation schemes step action frame content comment random sequence modulated rf signal 0x00 (each byte) f ch ? 0.1 mhz, cw signal f ch ? 0.25 mhz, cw signal 10 frame buffer access 0xff (each byte) f ch + 0.1 mhz, cw signal f ch + 0.25 mhz, cw signal
164 8168b-mcu wireless-02/09 AT86RF212 a.3 ? register description register 0x36 (tst_ctrl_digi) : register tst_ctrl_digi enables the continuous transmission test mode. table a-3. register 0x36 (tst_ctrl_digi) bit 7 6 5 4 name reserved reserved reserved reserved read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 name tst_ctrl_dig tst_ctrl_dig tst_ctrl_dig tst_ctrl_dig read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:4 ? reserved ? bit 3:0 ? tx_ctrl_dig these register bits enable continuous transmission: table a-4. continuous transmission register bits value description 0x0 continuous transmission disabled 0xf continuous transmission enabled tst_ctrl_dig 0x1 ? 0xe reserved
165 8168b-mcu wireless-02/09 AT86RF212 appendix b ? errata AT86RF212 rev. a no known errata.
166 8168b-mcu wireless-02/09 AT86RF212 references [1] ieee standard 802.15.4 tm -2006: wireless medium access control (mac) and physical layer (phy) specifications for low-rate wireless personal area networks (wpans) [2] ieee standard 802.15.4 tm -2003: wireless medium access control (mac) and physical layer (phy) specifications for low-rate wireless personal area networks (wpans) [3] ieee p802.15.4c tm /d6, november 2008: wireless medium access control (mac) and physical layer (phy) specifications for low-rate wireless personal area networks (lr-wpans): amendment 2: alternative physical layer extension to support one or more of the chinese 314-316 mhz, 430-434 mhz, and 779-787 mhz bands. [4] etsi en 300 220-1 v2.2.1 (2008-04): electromagnetic compatibility and radio spectrum matters (erm); short range devices (srd); radio equipment to be used in the 25 mhz to 1 000 mhz frequency range with power levels ranging up to 500 mw; part 1: technical characteristics and test methods [5] ansi / esd-stm5.1-2001: esd association standard test method for electrostatic discharge sensitivity testing ? human body model (hbm). [6] esd-stm5.3.1-1999: esd association standard test method for electrostatic discharge sensitivity testing ? charged device model (cdm). [7] nist fips pub 197: advanced encryption standard (aes), federal information processing standards p ublication 197, us department of commerce/nist, november 26, 2001
167 8168b-mcu wireless-02/09 AT86RF212 data sheet revision history rev. 8168b-mcu wireless-02/09 1. operation in the chinese 780 mhz band added 2. section 7.7.5 on clock jitter added 3. upd ate of table 7-15 and parameters in section 10 4. editorial changes rev. 8168a-avr-06/08 1. initial release
168 8168b-mcu wireless-02/09 AT86RF212 table of contents 1 overview .............................................................................................. 2 1.1 general circui t description .................................................................................... 2 2 pin confi guration................................................................................ 4 2.1 pin-out diagram...................................................................................................... 4 2.2 pin de scription ....................................................................................................... 4 3 applicati on circ uits .......................................................................... 10 3.1 basic applicat ion schematic ................................................................................ 10 3.2 extended feature set application schematic...................................................... 11 4 microcontro ller interface .................................................................. 13 4.1 over view............................................................................................................... 13 4.2 spi timing description......................................................................................... 14 4.3 spi pr otocol.......................................................................................................... 15 4.4 phy status information........................................................................................ 20 4.5 radio transceive r identification ........................................................................... 21 4.6 sleep/wake-up and trans mit signal (slp_tr)................................................... 22 4.7 interru pt logi c....................................................................................................... 24 5 operatin g modes............................................................................... 29 5.1 basic oper ating mode.......................................................................................... 29 5.2 extended operating mode ................................................................................... 41 6 functional d escripti on ..................................................................... 66 6.1 introduction ? ieee 802. 15.4-2006 fram e format .............................................. 66 6.2 frame filter .......................................................................................................... 70 6.3 frame check sequence (fcs) ............................................................................ 76 6.4 received signal streng th indicato r (rssi) .......................................................... 79 6.5 energy de tection (ed) ......................................................................................... 81 6.6 clear channel as sessment (cca)....................................................................... 83 6.7 listen before talk (lbt) ...................................................................................... 88 6.8 link quality indication (lqi) ................................................................................. 90 7 module d escription........................................................................... 92 7.1 physical layer modes .......................................................................................... 92 7.2 receiv er (rx) ....................................................................................................... 97 7.3 transmit ter (tx) ................................................................................................. 100 7.4 frame buffer....................................................................................................... 109 7.5 voltage regulator s (avreg, dvreg).............................................................. 111 7.6 battery moni tor (batmon) ................................................................................ 115
169 8168b-mcu wireless-02/09 AT86RF212 7.7 crystal oscillator (xosc) and clock output (clkm) ........................................ 117 7.8 frequency synt hesizer (pll)............................................................................. 122 7.9 automatic filt er tuning (ftn) ............................................................................ 127 8 radio transcei ver usage ............................................................... 129 8.1 frame rece ive procedure ................................................................................. 129 8.2 frame transmi t procedure ................................................................................ 130 9 extended f eature set ..................................................................... 131 9.1 security module (aes) ....................................................................................... 131 9.2 random numb er generator............................................................................... 138 9.3 differential output supporting so ftware controlled antenna diversity ............... 139 9.4 rx/tx indicator .................................................................................................. 141 9.5 rx frame ti me stamping.................................................................................. 143 9.6 frame buffer em pty indicator ............................................................................ 145 9.7 dynamic frame buffer protection ...................................................................... 146 9.8 configurable start-of -frame delimit er (sfd).................................................... 148 10 electrical characteris tics ............................................................. 149 10.1 absolute ma ximum ratings.............................................................................. 149 10.2 operatin g range .............................................................................................. 149 10.3 digital pin specifications .................................................................................. 149 10.4 digital interface ti ming characteristics............................................................ 150 10.5 general transcei ver specifications ................................................................. 151 10.6 transmitter ch aracteristics .............................................................................. 152 10.7 receiver characteristics .................................................................................. 153 10.8 current consumption specifications ................................................................ 154 10.9 crystal parame ter requirements ..................................................................... 154 11 register refere nce ....................................................................... 155 12 abbrevi ations ................................................................................ 158 13 ordering information .................................................................... 160 14 soldering in formation................................................................... 160 15 package thermal properties........................................................ 160 16 package dra wing ? 32qn2 ........................................................... 161 appendix a ? continuous tr ansmission t est mode ...................... 162 a.1 ? ov erview ......................................................................................................... 162 a.2 ? config uration................................................................................................... 162 a.3 ? register description........................................................................................ 164 appendix b ? errata........................................................................... 165
170 8168b-mcu wireless-02/09 AT86RF212 AT86RF212 rev. a .................................................................................................. 165 references.......................................................................................... 166 data sheet revi sion history ............................................................. 167 rev. 8168b-mcu wi reless-02/09 ............................................................................ 167 rev. 8168a-avr-06/08............................................................................................ 167 table of contents............................................................................... 168
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